Stacked Heterogeneous DRAM Cache for Low-Latency Tag Access
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Solution Overview
Problem
Conventional DRAM cache architectures face inefficiencies due to high latency in tag memory access and bus turnaround penalties, limiting cache bandwidth and overall performance.
Innovation Solution
A DRAM cache architecture with stacked, heterogeneous dies, featuring a dedicated low-latency tag DRAM die and capacity-optimized data DRAM dies, utilizing full-duplex signaling, embedded tag engines, and read-modify-write operations to reduce latency and eliminate bus turnaround, enabling rapid hit/miss determination and concurrent data transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional DRAM cache architecture is used, then cache capacity can be achieved, but tag memory access latency is high
Solution Approach 1:
The patent segments the DRAM cache into separate data DRAM dies and tag DRAM dies, with tag storage further divided into LRU tag storage and valid tag storage. This segmentation allows independent optimization of tag access paths, enabling low-latency tag retrieval through dedicated tag DRAM circuits that operate independently from data DRAM operations, thereby reducing tag memory access latency while maintaining cache bandwidth.
2Productivity
If bus turnaround is used for tag access, then tag memory can be accessed, but bus turnaround penalty reduces cache bandwidth
Solution Approach 1:
The patent introduces dedicated tag DRAM dies with full-duplex signaling interfaces as intermediaries between the processor and data DRAM dies. These tag DRAM dies handle tag access operations independently, eliminating the need for bus turnaround penalties associated with shared data paths. The full-duplex signaling enables simultaneous tag reads and data transfers, thereby increasing cache bandwidth while removing bus turnaround delays.
3Speed
If stacked heterogeneous dies are used, then latency is reduced and bandwidth enhanced, but device complexity increases
Solution Approach 1:
The tag DRAM die is designed with multi-functionality to handle various tag operations including LRU tag retrieval, valid tag storage, and full-duplex signaling simultaneously. The embedded tag engine within the tag DRAM die performs multiple functions (tag comparison, LRU management, valid bit tracking) in a unified structure, reducing the need for separate complex control logic and thereby managing device complexity while achieving low latency and high bandwidth.
4Productivity
If full-duplex signaling is implemented, then concurrent operations are enabled, but manufacturing complexity increases
Solution Approach 1:
The full-duplex signaling capability is implemented locally within the tag DRAM die structure, with dedicated signal paths for simultaneous read and write operations. The tag DRAM die incorporates localized full-duplex interfaces that enable concurrent tag access operations without requiring complex system-wide signaling changes. This localized implementation simplifies manufacturing by confining the complexity to a manageable component level rather than system level.
Data Source
AI summary
A high-capacity cache memory is implemented by multiple heterogenous DRAM dies, including a dedicated tag-storage DRAM die architected for low-latency tag-address retrieval and thus rapid hit/miss determination, and one or more capacity-optimized cache-line DRAM dies that render a net cache-line storage capacity orders of magnitude beyond that of state-of-the art SRAM cache implementations. The tag-storage die serves double-duty in some implementations, yielding rapid tag hit/miss determination for cache-line read/write requests while also serving as a high-capacity snoop-filter in a memory-sharing multiprocessor environment.