Stacked DRAM Cache with Dedicated Tag Die for Faster Hit Detection
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Solution Overview
Problem
Conventional DRAM cache architectures face inefficiencies due to high latency in tag memory access and bus turnaround penalties, limiting cache bandwidth and overall performance.
Innovation Solution
A DRAM cache architecture with stacked, heterogeneous dies, featuring a dedicated low-latency tag DRAM die and capacity-optimized data DRAM dies, utilizing full-duplex signaling and an embedded tag engine to enable concurrent operations, reducing row activation latency and eliminating bus turnaround penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional DRAM cache architecture is used, then cache capacity is achieved, but tag memory access latency is high
Solution Approach 1:
The patent segments the monolithic DRAM cache into separate data DRAM dies and tag DRAM dies stacked in different tiers. Tag memory is isolated on dedicated tag dies with direct TSV connections to the processor die, separating tag access paths from data access paths. This segmentation allows independent optimization of tag access latency without compromising data storage capacity.
Solution Approach 2:
The patent transitions from a two-dimensional planar cache architecture to a three-dimensional stacked architecture with vertical TSV interconnections. Tag DRAM dies are positioned in upper tiers with direct vertical connections to the processor, creating a hierarchical spatial arrangement that reduces tag access latency by eliminating horizontal bus traversal.
2Productivity
If conventional DRAM cache architecture is used, then cache storage capacity is maintained, but bus turnaround penalties reduce cache bandwidth
Solution Approach 1:
The patent segments memory access paths into dedicated tag access paths and data access paths. Tag DRAM dies handle only tag comparison and status operations, while data DRAM dies handle data transfer. This segmentation eliminates bus turnaround penalties by allowing tag operations and data operations to proceed independently on separate paths.
Solution Approach 2:
The patent introduces dedicated tag DRAM dies as intermediary structures between the processor and data DRAM dies. These tag dies perform tag comparison and hit/miss determination locally, acting as mediators that resolve memory access requests without requiring data to traverse the entire bus system, thereby reducing turnaround time.
3Duration of action of moving object
If stacked heterogeneous dies are used, then row cycle time is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the cache into specialized data DRAM dies and specialized tag DRAM dies that can be manufactured using optimized processes for their respective functions. Each die type can be fabricated independently with process optimizations tailored to its specific requirements, then stacked using TSV interconnections.
Solution Approach 2:
The patent designs the stacked architecture with standardized TSV interconnection interfaces and unified memory control logic that can accommodate different configurations of data and tag dies. This universal interface design allows flexible assembly of heterogeneous dies while maintaining manufacturing efficiency through standardized connection protocols.
Data Source
AI summary
A high-capacity cache memory is implemented by multiple heterogenous DRAM dies, including a dedicated tag-storage DRAM die architected for low-latency tag-address retrieval and thus rapid hit/miss determination, and one or more capacity-optimized cache-line DRAM dies that render a net cache-line storage capacity orders of magnitude beyond that of state-of-the art SRAM cache implementations. The tag-storage die serves double-duty in some implementations, yielding rapid tag hit/miss determination for cache-line read/write requests while also serving as a high-capacity snoop-filter in a memory-sharing multiprocessor environment.