Stacked DRAM Capacitor Arrays for Higher Capacitance Density
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Solution Overview
Problem
Current dynamic random access memory (DRAM) technologies face challenges in increasing capacitance without complicating the manufacturing process.
Innovation Solution
The design incorporates a double-sided top capacitor array stacked on a single-sided bottom capacitor array, with specific electrode and dielectric layer configurations, along with landing pads and contacts, to enhance capacitance and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked capacitors are used to increase capacitance, then total capacitance is improved, but manufacturing process complexity increases
Solution Approach 1:
The capacitor array is segmented into two distinct types: single-sided capacitors in the bottom array and double-sided capacitors in the top array. This segmentation allows each capacitor type to be optimized for its specific function while simplifying the overall manufacturing process by using standardized fabrication techniques for each segment rather than requiring complex integrated design.
Solution Approach 2:
The patent transitions from traditional single-layer capacitor structures to a three-dimensional stacked architecture with capacitors arranged in multiple layers (bottom and top arrays). This dimensional change increases the effective capacitance by utilizing vertical space while maintaining manufacturability through established semiconductor fabrication processes for multi-layer structures.
2Quantity of substance
If capacitor size is increased to improve capacitance, then total capacitance is improved, but device area increases
Solution Approach 1:
The patent resolves the area-capacitance tradeoff by transitioning from two-dimensional planar capacitor expansion to three-dimensional vertical stacking. The bottom and top capacitor arrays are positioned at different vertical levels, allowing increased total capacitance without proportionally increasing the device footprint area.
Solution Approach 2:
The double-sided capacitors in the top array are positioned above and around the single-sided capacitors in the bottom array, creating a nested three-dimensional structure. This nesting arrangement maximizes capacitance density by utilizing the vertical space between and around the capacitor structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases total capacitance, improves bit line sensing margin, and enhances retention performance while maintaining a manageable manufacturing process.
Implementation Method 1
A DRAM cell includes a metal-oxide semiconductor field effect transistor (MOSFET) and a capacitor
Implementation Method 2
each of the bottom capacitor structures includes a top electrode, a first dielectric layer surrounded by the top electrode, and a bottom electrode surrounded by the first dielectric layer and the top electrode
Data Source
AI summary
A dynamic random access memory includes an array region, a bottom capacitor array located in the array region, and a top capacitor array located in the array region and located on the bottom capacitor array. The bottom capacitor array is single-sided capacitor array. The top capacitor is a double-sided capacitor array.