Stacked DRAM-Capacitor Package Layout for Voltage Stability
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Solution Overview
Problem
Existing semiconductor package structures face challenges in miniaturization due to the larger size required by capacitor structures, which hinders the development of smaller, high-performance integrated circuits that demand higher currents at higher frequencies with lower power-supply voltages.
Innovation Solution
The integration of a capacitor die with dynamic random access memory (DRAM) dies, where the capacitor die includes a plurality of capacitor structures and conductive pillars electrically coupled to the DRAM die, surrounded by a molding material, allowing for increased capacitance without occupying more space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitor structures are added to provide decoupling capacitance, then power noise is reduced and voltage stability is improved, but the package size increases
Solution Approach 1:
The capacitor die is integrated within the semiconductor package structure, nesting the capacitor functionality inside the existing package footprint. The capacitor die is positioned below the DRAM die and surrounded by molding material, allowing capacitance to be provided without increasing the overall package area.
Solution Approach 2:
The capacitor structures utilize the vertical dimension by stacking the capacitor die below the DRAM die. This three-dimensional arrangement allows both the DRAM functionality and decoupling capacitance to coexist within the same package footprint, effectively using the Z-axis to resolve the area constraint.
2Reliability
If capacitor structures are enlarged to provide sufficient decoupling capacitance, then power noise reduction is improved, but the space available for other components is reduced
Solution Approach 1:
The capacitor functionality is segmented into a separate capacitor die with multiple capacitor structures arranged side-by-side. This segmentation allows the capacitor die to be optimized for capacitance density while the DRAM die maintains its own optimized layout, preventing either component from needing to be oversized.
Solution Approach 2:
The package structure uses a composite arrangement of different die types (capacitor die and DRAM die) within a single package. This composite structure allows each die to be optimized for its specific function while collectively providing both high capacitance and sufficient space for other components through the vertical stacking arrangement.
Data Source
AI summary
A semiconductor package structure includes a dynamic random access memory (DRAM) die, a capacitor die, and a molding material. The capacitor die is disposed below the DRAM die and includes a plurality of capacitor structures and a plurality of first conductive pillars. The capacitor structures are arranged side-by-side. The first conductive pillars are disposed over the capacitor structures and are electrically coupled to the DRAM die. The molding material surrounds the capacitor die and the DRAM die.