Stacked DRAM Capacitor Pillars for Density and Stability

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Solution Overview

Problem

The challenge in semiconductor fabrication is to reduce the size of capacitors while maintaining desired levels of capacitance, as thinner and taller capacitors become difficult to pattern and are prone to mechanical instability, such as tipping or toppling, during the formation process.

Innovation Solution

The method involves forming capacitors by stacking sections of pillars, with each fabrication process incrementally increasing the height without widening, and using electrically insulative spacers and interconnect material to stabilize and connect the pillars, forming a dense array that is mechanically stable and maintains capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If capacitors are made thinner and taller to reduce real estate consumption, then integration density is improved, but manufacturing precision deteriorates due to difficulty in patterning openings and filling with storage node material

Engineering Contradiction:
Improvereal estate consumptionVSAvoidpatterning precision
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

The capacitor structure is divided into multiple segments: a first capacitor storage node pillar, a first capacitor plate, a second capacitor storage node pillar, and a second capacitor plate. These segments are formed at different heights and connected through conductive interconnect material, allowing each segment to be manufactured separately with standard precision while achieving high overall density

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a conventional single-level capacitor structure to a multi-level vertical structure. Capacitor plates and storage nodes are stacked at different heights (first level and second level), utilizing the vertical dimension to increase capacitance density without increasing lateral footprint or compromising manufacturing precision

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of moving object

If capacitors are made thinner and taller to reduce real estate consumption, then integration density is improved, but reliability deteriorates due to mechanical instability and risk of tipping or toppling

Engineering Contradiction:
Improvereal estate consumptionVSAvoidmechanical stability
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The tall capacitor structure is segmented into multiple shorter pillars and plates at different heights. This segmentation reduces the aspect ratio of each individual component, improving mechanical stability while maintaining overall height for high density

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Conductive interconnect material acts as an intermediary, connecting the first and second capacitor storage node pillars. This interconnect material provides mechanical support and stabilization to the tall structures, preventing tipping or toppling while enabling electrical connection between levels

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP2215658B1Semiconductor constructions and methods of forming capacitors
Publication Date: 2017.08.09 MICRON TECHNOLOGY INC
  • EP2215658B1 patent drawingFigure 1
  • EP2215658B1 patent drawingFigure 2
  • EP2215658B1 patent drawingFigure 3

AI summary

Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of the capacitor may be formed to include a second storage node, a second dielectric material, and a second plate material. The first and second sections may be formed over a memory array region, and the first and second plate materials may be electrically connected to first and second interconnects, respectively, that extend to over a region peripheral to the memory array region. The first and second interconnects may be electrically connected to one another to couple the first and second plate materials to one another. Some embodiments include capacitor structures, and some embodiments include methods of forming DRAM arrays.