Stacked DRAM Cell Bit Line and Capacitor Integration
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Solution Overview
Problem
Conventional DRAMs face challenges in achieving high integration density and efficient data reading due to the limited capacitance ratio between the capacitor and the gate transistor, leading to errors and signal delays, especially with the use of vertical transistors which result in high resistance and heat generation.
Innovation Solution
A semiconductor memory device with a stack capacitor configuration where the bit line is formed over the stack capacitor, allowing for a simpler structure, higher integration, and reduced power consumption, with the source line optionally provided in parallel to the word line, and the off-state resistance of the cell transistor set to greater than 1×10^18Ω to minimize data rewriting needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the capacitance of the capacitor is made smaller than or equal to ten times the gate capacitance of the cell transistor, then the cell area can be reduced, but the margin of data reading becomes small leading to errors
Solution Approach 1:
The patent introduces a new spatial dimension by forming the bit line above the capacitor in a stacked configuration rather than in the planar plane. This vertical arrangement allows the bit line to be positioned in a different layer, enabling closer integration without increasing the planar cell area while maintaining sufficient capacitance ratio for reliable reading
2Area of stationary object
If vertical transistors are used to reduce cell area, then integration degree is improved, but resistance increases and heat is generated
Solution Approach 1:
The patent merges the bit line and capacitor into a stacked configuration where the bit line is formed directly above the capacitor. This integration reduces the need for separate high-resistance vertical transistor structures while maintaining compact cell area, thereby reducing power consumption and heat generation
3Ease of operation
If the bit line is placed in a floating state during reading, then data can be read through charge release, but signal delays occur due to capacitive coupling
Solution Approach 1:
The patent uses the capacitor as an intermediary element between the storage node and the bit line. The capacitor mediates the charge transfer process, allowing controlled charge release to the bit line while the stacked configuration minimizes parasitic capacitance, thereby reducing signal delays during reading operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances reading accuracy, reduces signal delays, and allows for higher integration density while minimizing power consumption and manufacturing steps, achieving reliable data storage and retrieval with reduced error rates.
Implementation Method 1
A DRAM stores data by accumulating electric charge in a capacitor of each memory cell
Implementation Method 2
reads the data by releasing the electric charge
Implementation Method 3
the word line 204a and the bit line 205 are capacitively coupled via the gate capacitance of the cell transistor 202, so that the potential of the bit line 205 varies
Data Source
AI summary
In a semiconductor memory device, one electrode of a capacitor is connected to a bit line, and the other electrode of the capacitor is connected to a drain of a cell transistor. A source of the cell transistor is connected to a source line. When a stack capacitor, for example, is used in this structure, one electrode of the capacitor is used as part of the bit line. An impurity region formed on the semiconductor substrate or a wiring parallel to a word line can be used as the source line; thus, the structure of a DRAM is simplified.