Stacked DRAM Cell Structure for Longer Charge Retention
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) devices face challenges with short charge retention times, leading to increased power consumption and leakage current due to the need for frequent data refresh, which affects the efficiency and reliability of mobile devices.
Innovation Solution
A semiconductor structure and formation method involving a substrate with multiple active layers, word lines, bit lines, and conductive contact plugs are used to create a 6F2 buried transistor and planar transistor architecture, where the second active layer between the gate dielectric and word line reduces leakage current and extends charge retention time, allowing for less frequent data refresh and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If a capacitor is used for data storage in DRAM, then data storage function is achieved, but charge retention time is short leading to high power consumption
Solution Approach 1:
The patent changes the fundamental storage mechanism from capacitor-based charge storage to transistor-based state storage. By utilizing the transistor's gate capacitance and channel state instead of a dedicated capacitor, the charge retention time is extended from milliseconds to seconds or longer, dramatically reducing refresh frequency and power consumption while maintaining data storage functionality
Solution Approach 2:
The patent extracts the storage function from the traditional capacitor component and integrates it into the transistor structure itself. The transistor's inherent gate capacitance is utilized as the storage element, eliminating the need for a separate capacitor and reducing the overall cell complexity while improving charge retention characteristics
2Reliability
If continuous data refresh is performed to prevent data loss, then data integrity is maintained, but power consumption and leakage current increase
Solution Approach 1:
The patent changes the storage mechanism to achieve much longer charge retention times by utilizing the transistor's gate oxide capacitance and controlled channel state. This extends data retention from millisecond-level (capacitor) to second-level or longer, reducing refresh operations from billions per second to millions per second, thereby maintaining data integrity while dramatically cutting power consumption
Solution Approach 2:
The transistor structure inherently maintains its stored state through its own physical properties (gate oxide capacitance and channel conductivity) without requiring external refresh operations. The device essentially refreshes itself by maintaining the charge state in the gate, reducing the need for continuous external intervention and associated power consumption
3Object-generated harmful factors
If physical size between second word line and conductive contact plug is increased, then leakage current is reduced, but device area increases
Solution Approach 1:
The patent utilizes vertical stacking to increase the physical separation between the second word line and conductive contact plug in the vertical dimension rather than expanding in the lateral plane. By stacking layers vertically (substrate, first active layer, gate dielectric layer, second active layer, second word line), the patent achieves greater distance for leakage current reduction while maintaining a compact planar footprint
Solution Approach 2:
The patent employs a nested layered structure where components are arranged in vertical tiers: the substrate contains first active areas with first word lines, above which sits the gate dielectric layer, then the second active layer with second word lines. This nesting in the vertical dimension allows increased spacing between critical elements without expanding the overall device area
Data Source
AI summary
Embodiments relate to a semiconductor structure and a formation method. The formation method includes: forming a first active layer on a side of the substrate; forming a first word line in each of the plurality of active areas; forming a first bit line and a conductive contact plug on a top of the first active layer; forming a gate dielectric layer on a side of the first active layer, a side of the first bit line, and a side of the conductive contact plug facing away from the substrate, respectively; forming a second active layer on a side of the gate dielectric layer facing away from the substrate; and forming a second bit line and a second word line on a side of the second active layer facing away from the substrate, where the second bit line and the second word line touch and connect the second active layer, respectively.