Stacked DRAM Logic Die ECC and DBI for High-Bandwidth Memory
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Solution Overview
Problem
Conventional memory devices, such as DRAM, face limitations in data bandwidth, power consumption, and die area utilization, particularly when stacking memory device dice, which can exacerbate issues like data retention errors and increase power consumption.
Innovation Solution
A memory system with stacked DRAM dice connected to a logic die using data bus inversion techniques, where the logic die performs error checking and correcting functions, and data encoding is used to maximize die area for memory capacity without significantly increasing power consumption or terminal count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wider internal data buses are used to transfer data to and from arrays with a higher bandwidth, then data bandwidth is improved, but the die area increases and write data must be serialized and read data deserialized at the memory device interface
Solution Approach 1:
The patent stacks multiple memory device dies vertically in a three-dimensional configuration, transitioning from planar expansion to vertical stacking. This allows the system to achieve higher bandwidth through multiple parallel data paths without proportionally increasing the die area of individual memory devices, as the vertical dimension provides additional data transfer channels.
Solution Approach 2:
The patent divides the memory system into multiple stacked memory device dies, each with its own data bus connections. This segmentation allows each die to maintain a manageable size while the collective system achieves high bandwidth through parallel operations across multiple dies, reducing the serialization/deserialization burden on individual devices.
2Reliability
If DRAM devices are refreshed frequently to prevent data retention errors, then data reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements error checking and correcting (ECC) codes that are prepared in advance and stored with the data in the memory devices. These pre-computed ECC codes enable the system to detect and correct data retention errors without requiring frequent refresh operations, thereby maintaining data reliability while reducing power consumption associated with frequent refreshing.
3Productivity
If multiple memory device dice are stacked in the same package to increase bandwidth, then data bandwidth is improved, but the number of terminals and die area for bond wire increase
Solution Approach 1:
The patent employs through-silicon vias (TSVs) to create vertical interconnects between stacked memory device dies, utilizing the vertical dimension for data transfer. This approach replaces the need for extensive bond wire routing and reduces the number of lateral terminals required, as TSVs provide direct through-conductor paths that simplify the terminal structure while enabling high-bandwidth data transfer.
4Quantity of substance
If feature sizes are scaled down to increase memory capacity, then storage capacity is improved, but manufacturing complexity and power consumption increase
Solution Approach 1:
The patent achieves increased memory capacity through vertical stacking of multiple memory device dies rather than relying solely on scaling down feature sizes within a single die. This three-dimensional architecture allows the system to scale capacity by adding more dies in the vertical direction, avoiding the manufacturing complexities and power consumption issues associated with aggressive feature size scaling while still achieving high storage capacity.
Data Source
AI summary
A memory system and method using at least one memory device die stacked with and coupled to a logic die by interconnects, such as through silicon vias. One such logic die includes an ECC system generating error checking and correcting (“ECC) bits corresponding to write data. The write data are transmitted to the memory device dice in a packet containing a serial burst of a plurality of parallel data bits. The ECC bits are transmitted to the memory device dice using through silicon vias that are different from the vias through which data are coupled. Such a logic die could also include a data bus inversion (“DBI”) system encoding the write data using a DBI algorithm and transmitting to the memory device dice DBI bits indicating whether the write data have been inverted. The DBI bits are transmitted using through silicon vias that are shared with the ECC bits when they are unused for transferring the ECC bits.