Stacked DRAM ECC Parity Layout for Fault-Tolerant Memory
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Solution Overview
Problem
Stacked memory devices face challenges due to defective memory chips, as the failure of one chip can render the entire stack defective, especially in volatile memories like SRAM and DRAM, where in-field repair capabilities are limited, leading to the discard of functional chips along with defective ones.
Innovation Solution
Incorporating an additional DRAM for storing parity data to implement a full stack ECC scheme, analogous to RAID 5 or RAID 6, allowing dynamic enablement or disablement of ECC and enabling substitution of the extra DRAM for a faulty one, thereby maintaining stack functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked memory devices are assembled with multiple memory chips, then memory density increases, but the risk of defective chips increases
Solution Approach 1:
The patent performs preliminary testing and identification of defective chips before final stack assembly. By conducting burn-in tests and electrical characterization on individual chips prior to stacking, the system can identify and exclude defective chips early in the manufacturing process, preventing them from compromising the entire stack's reliability while still allowing high-density assembly of verified good chips.
Solution Approach 2:
The patent changes the operational parameters of memory chips by adjusting voltage levels and operating conditions during testing and operation. By monitoring parameters such as leakage current, switching thresholds, and temporal behavior under varying voltages, the system can distinguish between marginal and defective chips, enabling selective assembly of chips that meet reliability criteria while maintaining high density.
2Reliability
If redundant rows and columns are added to replace defective bits, then reliability improves, but memory cell overhead increases
Solution Approach 1:
The patent segments the memory array into multiple independent banks or regions, each with its own redundancy resources. Instead of providing full redundancy across the entire memory array, each segment has localized redundant rows and columns that can be activated independently. This reduces the overall overhead compared to global redundancy while maintaining reliability through distributed fault coverage.
Solution Approach 2:
The patent implements partial redundancy by providing redundant rows and columns only for specific critical regions or for a subset of memory chips in the stack. Rather than over-provisioning the entire system with full redundancy, the system applies redundancy selectively where it is most needed, balancing reliability improvement with acceptable overhead.
3Reliability
If in-field repair is performed for individual memory chips, then reliability improves, but device complexity and cost increase
Solution Approach 1:
The patent implements self-service repair mechanisms where the memory system automatically detects defective chips or bits and activates pre-configured redundancy resources without external intervention. The system includes built-in diagnostic circuits that can identify failures and automatically switch to redundant resources, providing in-field repair capability without requiring complex external repair equipment or procedures.
Data Source
AI summary
The invention pertains to semiconductor memories, and more particularly to enhancing the reliability of stacked memory devices. Apparatuses and methods are described for implementing RAID-style error correction to increase the reliability of the stacked memory devices.