Stacked DRAM Capacitor Structure With Geared Electrodes
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Solution Overview
Problem
The charge storage capability of existing cylindrical double-sided capacitors in DRAMs below 20 nanometers does not meet the requirements for advanced memory devices.
Innovation Solution
A method and structure for a capacitor that includes a columnar bottom electrode with first gears and an annular top electrode with second gears, both surrounded by a dielectric layer, formed through a process involving stacked layers, via holes, and sacrificial layers to enhance capacitance and storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a cylindrical double-sided capacitor structure is used, then the manufacturing process is simple, but the charge storage capability is insufficient for advanced memory devices
Solution Approach 1:
The patent transitions from a traditional cylindrical capacitor structure to a planar capacitor structure with stacked layers. This dimensional change allows the capacitor to achieve larger effective area for charge storage while maintaining compatibility with standard semiconductor manufacturing processes. The stacked layer configuration enables increased capacitance without requiring deeper holes or more complex three-dimensional geometries.
Solution Approach 2:
The capacitor is divided into multiple stacked layers, each containing conductive layers and dielectric layers. This segmentation allows the total capacitance to be distributed across multiple parallel plates, effectively increasing the total charge storage capability while keeping each individual layer manufacturable using existing process technology.
2Quantity of substance
If the capacitor cross-sectional area is increased to enhance capacitance, then the charge storage capability improves, but the device complexity increases
Solution Approach 1:
The patent extracts the capacitor structure from its traditional cylindrical form and reconfigures it as a planar stacked structure. This extraction allows the capacitor to achieve larger effective area using horizontal stacking rather than vertical depth, reducing the complexity associated with forming and filling deep cylindrical holes while maintaining or increasing charge storage capability.
Solution Approach 2:
By changing from a vertical cylindrical structure to a horizontal stacked layer structure, the patent utilizes the planar dimension more effectively. This dimensional transformation increases the effective capacitor area without requiring proportionally increased device footprint or depth, thereby managing structural complexity while enhancing capacitance.
3Quantity of substance
If a stacked layer structure with multiple units is formed, then the capacitance increases, but the manufacturing precision requirements increase
Solution Approach 1:
The patent combines multiple conductive layers and dielectric layers into a unified stacked structure that functions as a single capacitor. This merging approach allows the formation of multiple capacitor units in parallel, increasing total capacitance while using standard deposition and etching processes that maintain reasonable precision requirements compared to more complex three-dimensional structures.
Data Source
AI summary
A capacitor structure and a method of preparing the same are provided. The method includes the followings. A substrate is provided. A stacked layer is formed on the substrate. A plurality of first via holes penetrating through the stacked layer are formed. The first via hole is filled with a conductive material to form a conductive pillar. A plurality of second via holes penetrating through the stacked layer are formed at a preset radius with the conductive pillar as an axis. The second via hole surrounds the conductive pillar circumferentially. The second via hole is filled with the conductive material to form an annular top electrode with a second gear.