Stacked 2T DRAM Cell With Nanosheet-FinFET Leakage Control
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Solution Overview
Problem
Current dynamic RAM (DRAM) cells face challenges in scaling due to strict transistor leakage requirements for data retention, resulting in poor area efficiency and low capacitance, particularly in the 2T DRAM cell configuration.
Innovation Solution
A stacked two-transistor (2T) DRAM cell is fabricated using a nanosheet field-effect transistor as the read transistor with high capacitance per footprint and a FINFET transistor based on oxide semiconductor material as the write transistor, with the transistors in an orthogonal configuration to enhance area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional DRAM cell design is used, then manufacturing simplicity is maintained, but area efficiency deteriorates and leakage current increases
Solution Approach 1:
The patent transitions from a planar 2T DRAM cell configuration to a stacked three-dimensional configuration. The first transistor is formed in a first plane and the second transistor is formed in a second plane vertically above the first plane, utilizing vertical stacking to improve area efficiency while managing device complexity through structured layering.
2Area of stationary object
If transistor size is reduced for scaling, then area efficiency improves, but leakage current increases due to strict retention requirements
Solution Approach 1:
By stacking transistors vertically in three dimensions rather than scaling planar transistors, the patent achieves higher area efficiency without the severe leakage penalties associated with aggressive planar scaling. The vertical configuration allows better control of leakage while maintaining compact footprint.
Solution Approach 2:
The patent segments the DRAM cell function into two separate transistors positioned in different vertical planes, with the first transistor handling one function and the second transistor handling another function. This segmentation allows independent optimization of each transistor for leakage control while achieving overall area efficiency.
3Area of stationary object
If planar configuration is used, then manufacturing is simpler, but area efficiency and capacitance per footprint are limited
Solution Approach 1:
The patent employs vertical stacking where the second transistor is positioned in a second plane above the first transistor in the first plane. This three-dimensional arrangement increases capacitance per footprint by utilizing vertical space, overcoming the limitations of planar configurations while maintaining structured manufacturing complexity.
Data Source
AI summary
A semiconductor structure includes a nanosheet field-effect transistor having a nanosheet stack structure, and a fin field-effect transistor having a set of vertical fins. Each of the vertical fins includes an oxide semiconductor material. The nanosheet field-effect transistor and the fin field-effect transistor are in a stacked configuration.