Stacked DRAM Master-Slave Die Layout for Lower Metallization Cost
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Solution Overview
Problem
Conventional stacked DRAM solutions using identical memory dies fail to optimize cost-effectiveness by incorporating unnecessary features in all dies, limiting their viability as standalone devices and missing opportunities for cost savings.
Innovation Solution
A stacked memory device comprising a master and slave memory die configuration, where the slave die lacks interface circuitry coupled to low-resistance metal layers, utilizing through-silicon-vias (TSVs) for interconnection, allowing for the same starting die to be fabricated into either a master, slave, or standalone memory die, reducing unnecessary metallization layers and enabling cost-effective production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If substantially identical memory dies are used in stacked configuration, then manufacturing simplicity is improved, but cost-effectiveness deteriorates due to unnecessary features in all dies
Solution Approach 1:
The patent applies local quality by differentiating features across different memory dies in the stack. Specifically, the master die includes interface circuitry coupled to low-resistance metal layers while slave dies do not. This allows each die to have the exact features needed for its role, eliminating unnecessary metallization layers in slave dies and reducing overall manufacturing costs while maintaining manufacturing simplicity through a standardized base process.
Solution Approach 2:
The patent segments the memory stack into master and slave dies with distinct functional characteristics. The master die contains full interface circuitry and low-resistance metal layers, while slave dies omit these features. This segmentation allows cost-effective production by only including expensive features where absolutely necessary, while still using the same starting die structure from the same mask set.
2Adaptability or versatility
If features are omitted on all dies to save cost, then manufacturing cost is reduced, but viability as standalone memory devices deteriorates
Solution Approach 1:
The patent achieves universality by designing the starting die structure and mask set to be versatile enough to produce multiple die types (master and slave) from the same fabrication process. The same base die can be configured as a standalone memory device or as part of a stacked configuration, depending on whether low-resistance metal layers and interface circuitry are included. This multi-functionality allows cost-effective production while maintaining standalone device viability.
3Reliability
If low-resistance metal layers are included in all dies, then electrical performance is improved, but manufacturing cost deteriorates
Solution Approach 1:
The patent applies local quality by selectively including low-resistance metal layers only in the master die where they are needed for interface circuitry operations. Slave dies in the stack omit these expensive metallization layers since they do not require interface functionality. This localized approach maintains electrical performance where necessary while significantly reducing manufacturing costs across the overall memory stack.
Solution Approach 2:
The patent extracts the low-resistance metal layers and interface circuitry from the slave dies, removing only the necessary components that contribute to cost without affecting the core memory functionality. This extraction allows slave dies to be produced more cheaply from the same starting structure, while the master die retains the full-featured configuration for optimal electrical performance.
Data Source
AI summary
A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.