Stacked DRAM Memory Layers to Improve Cell Ratio
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional DRAM devices face issues with reduced cell ratio and increased manufacturing costs due to the integration of memory and peripheral regions in the same device layer, leading to wasted substrate area and tightened process margins.
Innovation Solution
The memory regions and peripheral regions are formed in different device layers, with peripheral regions partially overlapping adjacent memory regions, allowing for improved cell ratio and larger memory capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the memory region and peripheral region are formed in the same device layer, then process integration is facilitated and word lines and bit lines can be directly connected to the peripheral region, but the usable substrate area is wasted and the cell ratio is reduced
Solution Approach 1:
The patent transitions from a planar arrangement where memory and peripheral regions share the same device layer to a three-dimensional stacked architecture. The memory region is formed in a first device layer while the peripheral region is formed in a second device layer positioned above it. This vertical stacking enables the memory array to occupy the entire substrate area in the first layer without being interrupted by peripheral circuits, thereby maximizing the cell ratio while maintaining direct connectivity through vertical interconnections.
2Device complexity
If the memory region and peripheral region are formed in the same device layer, then direct connection of word lines and bit lines to peripheral region is achieved, but process margin is tightened due to device shrinkage and circuit complexity
Solution Approach 1:
The patent divides the device into distinct functional layers: the first device layer contains the memory region with memory cells, while the second device layer contains the peripheral region with control circuits. This segmentation separates the high-density memory array from the control logic, allowing each layer to be optimized independently. The separation reduces the complexity of integrating both functions in a single layer and relaxes process margin requirements by eliminating the need to simultaneously accommodate both memory and peripheral structures at the same integration level.
3Adaptability or versatility
If peripheral region occupies areas between memory regions, then control circuits can be integrated, but the cell ratio of the DRAM device is reduced
Solution Approach 1:
The patent resolves the area conflict by moving the peripheral region to a different vertical level (second device layer) above the memory region in the first device layer. This three-dimensional arrangement allows the peripheral circuits to be fully integrated while occupying zero horizontal space in the memory plane. Consequently, the entire substrate area in the first layer is available for memory cells, maximizing the cell ratio while maintaining complete control circuit functionality in the stacked architecture.
Data Source
AI summary
A memory structure includes a substrate, a first device layer disposed on the substrate, a plurality of memory regions in the first device layer, a plurality of word lines and bit lines in the first device layer to control memory cells of the memory regions, a second device layer disposed between the substrate and the first device layer, and first peripheral regions and second peripheral regions in the second device layer, wherein in a top view, the first peripheral regions and the second peripheral regions respectively partially overlap adjacent two of the memory regions.