Stacked DRAM-NAND Memory Architecture for Speed-Density Tradeoffs
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Solution Overview
Problem
Existing memory technologies, such as DRAM, NAND, and MRAM, have significant limitations in terms of density, speed, and cost, and current solutions that combine NAND and DRAM at the package level retain inefficiencies due to separate interfaces.
Innovation Solution
A stacked memory architecture that combines DRAM with multiple layers of NAND using direct bonding interconnects (DBI), allowing for high-bandwidth, high-pincount interconnects and enabling the RAM to store logic for the NVM or include a separate non-volatile logic layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM is used for memory storage, then speed is improved, but density deteriorates
Solution Approach 1:
The memory system is segmented into multiple functional layers: volatile DRAM layers for fast access and non-volatile memory layers for high density storage. Each layer performs specialized functions, with the DRAM layer handling active data and the NVM layer providing bulk storage capacity.
Solution Approach 2:
The patent transitions from planar 2D memory architecture to a three-dimensional stacked architecture. Multiple DRAM and NVM layers are vertically stacked and interconnected through through-silicon vias (TSVs), enabling high-density integration while maintaining fast access speeds through the volatile layers.
2Quantity of substance
If NAND memory is used for storage, then density is improved, but speed deteriorates
Solution Approach 1:
The memory system segments storage functions between volatile and non-volatile layers. The NVM layer provides high-density storage for data that does not require immediate access, while the DRAM layer handles frequently accessed data, creating a hierarchical storage architecture.
Solution Approach 2:
The volatile DRAM layer acts as an intermediary between the high-speed external interface and the high-density but slower NVM layer. Data is transferred from NVM to DRAM for processing, and results are written back to NVM, optimizing overall system performance.
3Adaptability or versatility
If NAND and DRAM are combined at package level, then versatility is improved, but device complexity deteriorates
Solution Approach 1:
Multiple DRAM and NVM dies are merged into a single integrated memory stack using advanced packaging techniques. The layers are vertically stacked and interconnected through TSVs, creating a unified memory system that functions as a single device rather than separate packaged components.
Solution Approach 2:
The stacked memory architecture provides multi-functionality by integrating different memory types (DRAM and NVM) with different characteristics into a single system. This enables the memory to serve multiple functions: high-speed caching, bulk storage, and hierarchical data management, all within one device.
Data Source
AI summary
The present disclosure provides for a stacked memory combining RAM and one or more layers of NVM, such as NAND. For example, a first layer of RAM, such as DRAM, is coupled to multiple consecutive layers of NAND using direct bonding interconnect (DBI®). Serialization and overhead that exists in periphery of the NVM may be stripped to manage the data stored therein. The resulting connections between the RAM and the NVM are high bandwidth, high pincount interconnects. Interconnects between each of the one or more layers of NVM are also very dense.