Stacked DRAM and Resistive Memory Integration
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Solution Overview
Problem
Next-generation semiconductor memory devices require improved integration of different memory technologies with varying operating characteristics on a single substrate, while maintaining high performance and low power consumption.
Innovation Solution
A semiconductor device design featuring a first memory section with DRAM cell arrays and a second memory section with variable resistance memory cell arrays, both integrated on a substrate with distinct peripheral circuit sections and wiring patterns, allowing for vertical stacking and efficient data storage with different operating characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different memory technologies (DRAM and variable resistance memory) are integrated on a single substrate, then data storage capabilities and operational efficiency are enhanced, but device complexity increases
Solution Approach 1:
The substrate is divided into distinct first and second memory sections, each dedicated to a specific memory technology (DRAM and variable resistance memory respectively). This segmentation allows each memory type to operate independently with its own peripheral circuits, reducing interference while maintaining integration benefits
Solution Approach 2:
The patent employs vertical stacking where the second memory section is positioned above the first memory section in the vertical dimension. This three-dimensional arrangement increases storage density and integrates multiple memory technologies without expanding the planar footprint, thereby managing device complexity
2Productivity
If memory cells with different operating characteristics are integrated, then performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
Each memory section is designed with local optimization for its specific memory technology. The first memory section contains DRAM cells with capacitors optimized for volatile storage, while the second memory section contains variable resistance elements optimized for non-volatile storage. Each section has its own peripheral circuits tailored to its operating characteristics, allowing high performance while managing manufacturing complexity through localized design
3Quantity of substance
If vertical stacking is implemented, then integration density is improved, but wiring complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking. The second memory section and its peripheral circuits are positioned above the first memory section, utilizing the vertical dimension to increase integration density. This approach consolidates multiple memory technologies within a compact volume while managing wiring complexity through systematic interconnection design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the creation of a highly integrated semiconductor device with improved performance and low power consumption by effectively combining DRAM and variable resistance memory technologies, enhancing data storage capabilities and operational efficiency.
Implementation Method 1
a material whose resistance differs depending on an applied electric current or voltage and whose resistance is maintained even if the applied electric current or voltage is interrupted
Implementation Method 2
each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor
Data Source
AI summary
A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate; and a second memory section and a wiring section that are stacked on the second peripheral circuit section, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, and the wiring section includes a plurality of line patterns, wherein the line patterns and the second memory cells are higher than the capacitor with respect to the substrate.