Stacked DRAM with Shared Control Lines
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Solution Overview
Problem
Existing double stacked DDR3 memory devices require separate control lines for each chip, making them difficult to integrate and access, as they are treated as separate components, often leading to design challenges and incompatibility with processors due to the lack of required control lines.
Innovation Solution
A memory device design where two synchronous dynamic random access memory chips are stacked with an interconnecting network that ties control and address signals together, ensuring equal trace lengths for all signals, allowing a single set of control lines to be used, thus simplifying integration and access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two memory chips are stacked in a single package with separate control lines for each chip, then the memory capacity is doubled, but the device complexity increases and integration becomes difficult
Solution Approach 1:
The patent merges the control lines for two separate memory chips into a single shared control line structure. The interconnecting network combines control signals from both chips so that a single set of control lines can be used to control both memory devices, thereby reducing the overall complexity while maintaining doubled capacity
Solution Approach 2:
The control lines are designed to serve multiple functions by controlling both memory chips simultaneously through the interconnecting network. The same control lines that would traditionally control only one chip are made universal to control both chips in the stacked configuration
2Quantity of substance
If two memory chips are stacked with separate control lines, then the memory capacity is doubled, but the ease of manufacture decreases due to routing requirements
Solution Approach 1:
The patent simplifies manufacturing by merging control line routing requirements into a single set of control lines that serve both memory chips. This eliminates the need for separate routing for each chip's control lines, making board layout easier while achieving doubled capacity
3Quantity of substance
If processors lack the required number of DRAM control lines, then the memory capacity can be doubled with stacked chips, but the adaptability decreases due to incompatibility with standard processors
Solution Approach 1:
The control lines are designed to be universal and compatible with standard processor interfaces. By merging control lines and designing them to function as a single set of control signals, the memory device becomes adaptable to standard processors without requiring additional or specialized control lines
4Reliability
If trace lengths for chip signals are made equal, then signal integrity is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The interconnecting network acts as an intermediary that compensates for trace length variations. By designing the network to equalize effective trace lengths, it maintains signal integrity without requiring extremely precise manufacturing control of individual trace lengths
Data Source
AI summary
A double density memory device including two synchronous dynamic random access memory chips, each having multiple data (DQ) signals, multiple address signals and multiple control signals. The chips are mounted in a package that provides interconnection terminals for conducting electrical signals to and from the memory chips. An interconnecting network is contained within the package to provide paths for electrically connecting the chip contact pad on each chip corresponding to a specific control or address signal to one interconnection terminal for that signal for both chips so that the control and address signals for the two chips are tied together. For each DQ signal, the chip contact pad on each chip corresponding to that DQ signal is connected by the interconnecting network to a separate interconnection terminal. The trace length between a chip contact pad and the interconnection terminal to which it connects for each signal is substantially the same.