Stacked DRAM Communication Using Snooped Mode Commands
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Solution Overview
Problem
Existing technologies face challenges in efficiently managing communication and command handling within stacked integrated circuit die structures, particularly in high-bandwidth memory (HBM) stacks, leading to inefficiencies and limitations in data transfer and command execution.
Innovation Solution
Implementing a processor die that snoops commands and uses through-silicon via (TSV) connections to manage data and control signals within a stack of DRAM and logic dies, allowing selective isolation and re-coupling of memory devices based on mode setting commands, enabling efficient communication and data management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a processor die is integrated into the DRAM stack, then data transfer efficiency is improved, but command handling complexity increases
Solution Approach 1:
The command handling functionality is segmented between the processor die and DRAM dies. The processor die contains command routing logic that intercepts and routes commands, while individual DRAM dies contain snoop logic to handle specific command types locally. This segmentation allows the processor to manage overall command flow without requiring full command processing capability in every DRAM die, reducing overall system complexity while maintaining high data transfer efficiency.
Solution Approach 2:
The processor die acts as an intermediary between the external interface and the DRAM dies. It receives commands from the external interface, determines which DRAM die should handle each command, and routes them accordingly. This intermediary role simplifies command handling by centralizing the decision-making logic in the processor die while allowing individual DRAM dies to focus on executing their specific command types.
2Quantity of substance
If multiple DRAM dies are stacked together, then memory capacity is increased, but signal propagation control becomes more difficult
Solution Approach 1:
Each DRAM die is equipped with snoop logic that is specifically configured to recognize and respond to particular command types. This local quality approach allows each die to have specialized handling capabilities rather than requiring all dies to process all command types. The processor die further enhances this by routing commands to the appropriate die based on the command type, thereby simplifying signal propagation control while maintaining high memory capacity through the stacked architecture.
3Speed
If through-silicon via connections are used to interconnect stacked dies, then data transfer speed is improved, but manufacturing precision requirements increase
Solution Approach 1:
The through-silicon via connections are designed to serve multiple functions: they carry data signals between dies, provide command routing pathways, and enable power and ground connections. By making the TSV infrastructure multi-functional, the patent reduces the need for separate dedicated structures for each function, thereby reducing overall manufacturing complexity and precision requirements while maintaining high data transfer speeds through the same physical pathways.
Data Source
AI summary
An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die has a base logic die and one or more custom logic or processor die. The processor logic die snoops commands sent to and through the stack. In particular, the processor logic die may snoop mode setting commands (e.g., mode register set—MRS commands). At least one mode setting command that is ignored by the DRAM in the stack is used to communicate a command to the processor logic die. In response the processor logic die may prevent commands, addresses, and data from reaching the DRAM die(s). This enables the processor logic die to send commands/addresses and communicate data with the DRAM die(s). While being able to send commands/addresses and communicate data with the DRAM die(s), the processor logic die may execute software using the DRAM die(s) for program and/or data storage and retrieval.