Stacked DRAM-SRAM LLC Layout for Hot Compute Dies
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in integrating dynamic random-access memory (DRAM) with static random-access memory (SRAM) due to temperature envelope limitations of DRAM on hotspots on central processing units (CPU)/graphics processing units (GPU) in system-on-chip (SoC) applications, hindering the implementation of high-capacity, low-latency memory solutions for last-level-cache (LLC).
Innovation Solution
A stacked system-on-chip (SoC) design is implemented, where a DRAM die is stacked on a compute logic die with integrated SRAM partitions, and a memory controller is coupled between these partitions and the DRAM bus, utilizing a network-on-chip (NoC) controller to enhance data arbitration and cooling, thereby allowing placement of LLC-DRAM on hot CPU/GPU logic dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM is integrated on hotspots of CPU/GPU in SoC, then memory capacity and integration density are improved, but temperature envelope limitations prevent reliable operation
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking by placing the DRAM die directly on top of the CPU/GPU die. This vertical arrangement allows the memory to be positioned in a different spatial dimension, enabling closer proximity to the heat source while maintaining operational integrity through direct thermal coupling to the heatsink structure.
Solution Approach 2:
The patent introduces a heatsink structure as an intermediary thermal management component between the hot compute logic and the DRAM. This mediator actively removes heat from the DRAM region, enabling the memory to operate within its temperature envelope even when positioned on the hotspots of the CPU/GPU.
2Quantity of substance
If DRAM cell footprint is reduced for higher density, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
By moving to three-dimensional stacking, the patent achieves higher effective density without further reducing the lateral footprint of individual DRAM cells. The vertical arrangement provides additional density through layering, allowing larger, more manufacturable cell designs while still achieving high overall integration density.
3Speed
If SRAM is used for cache memory, then speed and power efficiency are improved, but area and scalability are limited by transistor roadmap
Solution Approach 1:
The patent merges SRAM and DRAM technologies in a hybrid cache architecture. The SRAM provides fast access for frequently used data, while the DRAM stacked on the compute logic provides additional capacity. This combination allows the system to achieve both the speed characteristics of SRAM and the density/scalability of DRAM within the same cache hierarchy.
Data Source
AI summary
A stacked system-on-chip (SoC) is described. The stacked SoC comprises a first memory die comprising a dynamic random-access memory (DRAM). The stacked SoC also comprises a compute logic die. The compute logic die comprises a static random-access memory (SRAM) comprising a first SRAM partition and a second SRAM partition. The first memory die is stacked on the compute logic die. The compute logic die comprises a memory controller. The memory controller is coupled between the first SRAM partition and the second SRAM partition. Additionally, the memory controller is coupled to a DRAM bus of the first memory die.