Stacked DRAM Data Placement Using Thermal Gradient Prediction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In stacked memory-processor architectures, processor-generated heat affects the performance of volatile DRAMs by increasing their refresh rates, leading to delayed data access.
Innovation Solution
A method and apparatus that leverage software hints indicating future processor usage to manage data in memory by predicting thermal gradients and selecting or migrating data to lower-temperature memory locations, using temperature sensors and memory allocation logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the refresh rate of DRAM storage banks is increased to maintain data integrity at higher temperatures, then data reliability is improved, but data access delay increases and processor performance deteriorates
Solution Approach 1:
The system performs preliminary thermal gradient prediction based on software hints indicating future processor usage patterns. Before data access is needed, the system predicts which memory locations will experience thermal gradients and proactively migrates data to cooler memory locations in advance. This preliminary action ensures data is already in optimal locations when needed, avoiding access delays while maintaining data integrity.
Solution Approach 2:
The memory system is divided into multiple storage banks with different thermal characteristics. The system segments data across these banks based on predicted thermal gradients, placing frequently accessed data in cooler banks. This segmentation allows different parts of memory to operate at different refresh rates based on their specific thermal conditions, improving overall system performance while maintaining data reliability.
2Productivity
If data is migrated to different memory locations to avoid thermal gradients, then data access performance is improved, but system complexity increases
Solution Approach 1:
The system uses software hints from the application code itself to drive thermal gradient prediction and data migration decisions. The hints embedded in the software provide information about future processor usage patterns, allowing the memory management system to make intelligent decisions without requiring complex external monitoring or control mechanisms. This self-service approach improves data access performance while limiting the increase in system complexity.
Solution Approach 2:
The system changes the parameter of memory location selection based on predicted thermal gradients. Instead of using fixed or random memory allocation, the system dynamically selects memory locations based on predicted temperature conditions and software usage patterns. This parameter change enables performance optimization while the prediction-based approach keeps the control logic relatively simple.
3Productivity
If thermal gradient prediction is performed to optimize memory location selection, then data access efficiency is improved, but processing overhead increases
Solution Approach 1:
Thermal gradient prediction is performed in advance based on software hints about future processor usage, rather than continuously during operation. This preliminary prediction allows the system to prepare optimal memory locations before data access is needed, improving efficiency while minimizing the frequency and energy cost of prediction operations.
Solution Approach 2:
The system extracts only the essential information needed for thermal gradient prediction from the software hints, rather than analyzing complete processor execution traces. By taking out only the relevant usage patterns, the system reduces processing overhead while maintaining the ability to make accurate predictions for optimizing data access efficiency.
Data Source
AI summary
Methods and apparatus manage data in memories disposed in a stacked relation with respect to one or more processors. The method includes receiving at least one hint indicating future processor usage of a software component, where the future processor usage is indicative of future usage of the one or more processors when executing the software component or a code section of the software component. In some implementations, the method includes selecting a memory location in the memories for data used by the software component based on the hint.