3D Stacked DRAM Chip Structure With Through-Via Bitline Connection
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing the size of elements while maintaining performance, particularly in forming reliable and stable reduced-size elements in dynamic random access memory (DRAM) systems.
Innovation Solution
The semiconductor device incorporates a lower chip structure with memory areas, bit lines, and complementary bit lines, along with an upper chip structure featuring a sense amplifier array region and through-vias that electrically connect the bit lines and complementary bit lines, enhancing integration and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If element size is reduced to improve integration density, then the degree of integration is improved, but manufacturing precision and reliability deteriorate
Solution Approach 1:
The patent transitions from planar 2D integration to 3D vertical integration by stacking memory cell regions across multiple semiconductor substrates. This dimensional change allows continued increase in integration density without further reducing individual element sizes, thereby avoiding the manufacturing precision problems that arise at smaller dimensions.
Solution Approach 2:
The memory device is divided into multiple semiconductor substrates, each containing memory cell regions with bit lines and word lines. This segmentation allows each substrate to be manufactured and tested independently before assembly, improving overall manufacturing precision while achieving high integration density through vertical stacking.
2Quantity of substance
If element size is reduced to improve integration density, then the degree of integration is improved, but stability and reliability deteriorate
Solution Approach 1:
By moving to 3D vertical stacking, the patent achieves higher integration density without further miniaturizing individual memory elements. This maintains element stability and reliability while increasing capacity, as each element retains its original optimized dimensions and performance characteristics.
Solution Approach 2:
Each memory cell region on each substrate is independently optimized with appropriate element sizes and structures for reliable operation. The local quality of each element is preserved while the overall system achieves high integration through vertical arrangement, ensuring both reliability and density.
3Quantity of substance
If multiple chip structures are stacked to improve integration, then the degree of integration is improved, but device complexity increases
Solution Approach 1:
The patent employs universal interconnection structures where through-substrate vias and bonding pads serve multiple functions across different substrate layers. The same via structures provide electrical connections between corresponding bit lines and word lines on adjacent substrates, simplifying the overall interconnection architecture despite the multi-layer complexity.
Solution Approach 2:
Multiple interconnection functions are merged into unified structures. Through-substrate vias simultaneously provide mechanical alignment, electrical connection, and structural support across stacked substrates. Bonding pads on adjacent substrates are merged through direct bonding to create integrated interconnection pathways, reducing the number of separate components needed.
Data Source
AI summary
A semiconductor device includes a lower chip structure, and an upper chip structure on the lower chip structure. The lower chip structure includes a memory structure, a lower interconnection structure electrically connected to the memory structure, and a lower bonding pad electrically connected to the lower interconnection structure. The upper chip structure includes an upper base, a peripheral transistor on the upper base, a first upper interconnection structure electrically connected to the peripheral transistor, on the upper base, a through-via penetrating through the upper base and electrically connected to the first upper interconnection structure, an upper bonding pad bonded to the lower bonding pad, below the upper base, and an intermediate connection structure electrically connecting the upper bonding pad and the through-via, between the upper base and the lower chip.