Stacked DRAM Timing Alignment Using a Logic Die
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Solution Overview
Problem
Conventional memory devices, such as DRAM, face limitations in data bandwidth due to signal timing skews between stacked memory device dice, which complicates data transfer and reduces system performance, especially with increasing operating speeds and the use of multi-core processors.
Innovation Solution
A memory system with a logic die that implements timing correction circuitry to align read data signals from multiple DRAM dice, using a wide bus and through-silicon vias to connect the dice, and adjusts strobe signals to synchronize data transfer without requiring extensive additional terminals or area reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory device dice are stacked to increase bandwidth, then data bandwidth is improved, but signal timing skews worsen between stacked devices
Solution Approach 1:
A logic die is introduced as an intermediary component between the processor and multiple stacked memory device dice. The logic die receives data from one memory device and redistributes it to multiple memory devices, thereby managing timing skews and enabling increased bandwidth without requiring precise timing alignment across all stacked devices.
2Manufacturing precision
If timing adjustment circuitry is added to correct signal skews, then timing alignment is improved, but device complexity increases
Solution Approach 1:
The logic die performs multiple functions: it acts as a buffer, a timing adjustment device, and a data redistribution hub. By consolidating these functions into a single component rather than adding separate timing adjustment circuitry to each memory device, the solution improves timing alignment while minimizing increases in overall device complexity.
3Manufacturing precision
If additional terminals are added for timing adjustments, then timing control is improved, but available area for memory capacity decreases
Solution Approach 1:
Timing control functionality is extracted from the memory device dice and relocated to the logic die. This extraction allows the memory device dice to maintain their existing terminal configurations for data transfer, while the logic die handles timing control separately, thereby preserving maximum area for memory capacity in the stacked devices.
4Quantity of substance
If feature size is reduced to increase capacity, then storage capacity is improved, but manufacturing precision requirements worsen
Solution Approach 1:
Instead of increasing storage capacity by reducing feature sizes in a single plane, the solution stacks multiple memory device dice vertically in the third dimension. This dimensional transition allows capacity expansion without requiring smaller feature sizes, thereby avoiding worsened manufacturing precision requirements.
Data Source
AI summary
A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.