Stacked DRAM TSV Layout for Die Failure Isolation

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Solution Overview

Problem

Existing DRAM devices face challenges in efficiently accessing multiple dies in a stack without interference from failed components, leading to communication failures and increased power consumption.

Innovation Solution

The implementation of through-silicon via (TSV) connections for vertical data and control signal transmission, along with unique chip identification numbers and non-overlapping data signal connections, allows for independent communication between DRAM dies, enabling concurrent access and mitigating power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple dies are stacked vertically to increase memory capacity, then the memory density is improved, but the reliability of data communication between dies deteriorates due to potential TSV connection failures and die failures

Engineering Contradiction:
Improvememory capacityVSAvoiddata communication reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The data signal connections are segmented into separate, non-overlapping sets for each die in the stack. Each die has its own dedicated TSV connections to the base die, preventing failure propagation between dies and ensuring that a failure in one die does not disrupt communication for other dies.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The base die acts as an intermediary that receives and routes data signals from external interfaces to the appropriate stacked dies. The base die includes buffer circuits that mediate signal transmission, ensuring reliable communication even when multiple dies are connected through shared TSV structures.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a failing die is isolated to prevent error propagation, then the reliability is improved, but the productivity deteriorates due to reduced accessible memory capacity

Engineering Contradiction:
Improveerror isolationVSAvoidaccessible memory capacity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory stack is segmented into independently addressable dies, each with separate connection paths through non-overlapping TSV sets. This segmentation allows the system to address and access individual dies or combinations of dies, enabling selective isolation of failed components while maintaining access to functional memory capacity.

Inventive Principle:
Principle #1Segmentation

3Reliability

If separate TSV connections are used for each die to prevent failure propagation, then the reliability is improved, but the device complexity increases due to additional connection structures

Engineering Contradiction:
Improvefailure isolationVSAvoidTSV connection structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The base die serves multiple functions: it acts as the primary interface for external communication, provides signal buffering and conditioning, and routes data to multiple stacked dies. This multi-functionality reduces the need for additional dedicated control structures at each die level, offsetting the complexity of having separate TSV connection sets.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12610862B2Reliability for DRAM device stack
Publication Date: 2026.04.21 RAMBUS INC
  • US12610862B2 patent drawing
  • US12610862B2 patent drawing
  • US12610862B2 patent drawing

AI summary

An interconnected stack of Dynamic Random Access Memory (DRAM) die has a base die and DRAM dies. The base die is interconnected vertically with the DRAM dies using through-silicon via (TSV) connections that carry data and control signals throughout the stack. The data signals of the DRAM dies are interconnected vertically to the base die using separate, non-overlapping, sets of TSVs. In a first configuration, each die in the stack is accessed using unique chip identification numbers. In a second configuration, a single chip identification number is used to access two or more dies in the stack. At least one bit of the chip identification number may be used in determining the row being accessed. Data communicated with dies in the stack may be communicated with the base die using non-overlapping sets of data signal connections.