Stacked DRAM Package with Aligned Active and Passive TSVs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current package-on-package (PoP) memory systems face challenges in reducing wirebond density, minimizing losses, and increasing channel bandwidth due to limitations in interconnect density and efficiency.
Innovation Solution
The implementation of a two-tiered windowed ball grid array (BGA) package with through-silicon vias (TSVs) that connect stacked DRAM dies, allowing for reduced wirebond length and density, and utilizing active and passive TSVs to enhance interconnect efficiency between integrated circuit dies and the BGA package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional wirebond interconnects are used in PoP memory systems, then ease of manufacture is maintained, but wirebond density is high causing increased losses and reduced channel bandwidth
Solution Approach 1:
The patent transitions from planar wirebond interconnects to three-dimensional TSV-based vertical interconnects. Through-silicon vias enable signals to travel vertically through the substrate rather than along the surface, reducing the number of wirebonds needed and minimizing signal loss by shortening the interconnect path length.
Solution Approach 2:
The patent replaces the mechanical wirebonding process with a TSV-based interconnect structure. Instead of mechanically attaching wirebonds to pads, the design uses etched vias filled with conductive material to create direct electrical pathways through the substrate, eliminating the need for wirebond density optimization.
2Productivity
If wirebond density is reduced to minimize losses, then channel bandwidth increases, but manufacturing complexity increases
Solution Approach 1:
The TSV structures are pre-formed in the substrate before die stacking, creating ready-made vertical interconnect pathways. This preliminary preparation eliminates the need for complex post-assembly wirebonding operations and simplifies the manufacturing process while enabling high channel bandwidth through efficient vertical signal routing.
Solution Approach 2:
The TSV structures serve as intermediary elements between the memory dies and the package substrate. These pre-formed vias act as mediators that facilitate electrical connections without requiring complex wirebonding operations, thus maintaining ease of manufacture while achieving high productivity through increased channel bandwidth.
3Reliability
If aligned active and passive TSVs are used, then interconnect efficiency increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent differentiates between active TSVs (connected to active circuitry) and passive TSVs (not connected to active circuitry). This local quality differentiation allows for optimized alignment strategies where only critical active TSVs require high-precision alignment, while passive TSVs can tolerate greater misalignment, thus maintaining interconnect efficiency without excessively stringent manufacturing precision requirements.
Solution Approach 2:
The design uses both aligned and misaligned TSV configurations strategically. Active TSVs are precisely aligned to ensure reliable electrical connections, while passive TSVs can be misaligned to simplify manufacturing. This partial alignment approach maintains necessary interconnect efficiency while reducing overall manufacturing precision requirements.
Data Source
AI summary
Disclosed is a package-on-package (PoP) assembly comprises a two-tiered windowed ball grid array (BGA) and a system on a chip (SoC) package. Window openings in the two tiers of the BGA are of different sizes to allow for wirebond landing pads on the first tier. A DRAM die is mounted to the BGA flipped over (i.e., wirebond pads facing the BGA package.) The DRAM die is wirebonded through the window in the BGA. For multi-channel systems and higher memory capacity, the DRAM die will have low-cost through-silicon vias (TSVs) that connect to stacked DRAM die(s). The stacked DRAM dies may be offset or rotated to align active TSVs with passive TSVs thereby enabling unique connections to certain DRAM dies in the stack.