Stacked DRAM With Vertical Conduction Traces
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Solution Overview
Problem
Conventional dynamic random access memory (DRAM) faces challenges in achieving high integration density due to increased process complexity and yield reduction when forming capacitors with high aspect ratios, leading to issues like capacitor leaning and storage node bridges between adjacent capacitors.
Innovation Solution
A stacked DRAM structure is implemented, where unit memory arrays are arranged on multiple substrates with vertical conduction traces connecting them, allowing for a sense amplifier region and word line driver regions to be positioned in a way that reduces the die size and maintains regular intervals for bit and word lines, enhancing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the area of capacitor is reduced to increase integration density, then the number of memory cells per unit area increases, but the capacitance decreases and the aspect ratio of capacitor increases leading to manufacturing defects
Solution Approach 1:
The patent transitions from planar (2D) capacitor arrangement to three-dimensional (3D) stacked architecture. Memory arrays are formed on multiple substrates stacked vertically, with through-substrate vias providing electrical connections between layers. This vertical stacking enables higher integration density without reducing individual capacitor area, thereby maintaining manufacturing quality while increasing storage capacity.
Solution Approach 2:
The memory device is divided into multiple independent substrates stacked together, each substrate containing complete memory arrays with capacitors, transistors, and interconnect structures. This segmentation allows each layer to be manufactured separately with controlled capacitor dimensions, avoiding the need to reduce capacitor area while achieving high density through vertical integration.
2Quantity of substance
If capacitors are made with high aspect ratio to compensate for reduced area, then the capacitance is maintained, but process complexity increases and yield decreases
Solution Approach 1:
Instead of increasing capacitor height (vertical dimension within single substrate) to maintain capacitance, the patent distributes capacitors across multiple substrates in the vertical stacking direction. Each capacitor maintains its original dimensions and aspect ratio on its respective substrate, eliminating high aspect ratio formation complexity while achieving equivalent total capacitance through parallel arrangement across layers.
3Quantity of substance
If horizontal downscaling is continued to increase density, then more memory cells fit in the same area, but technical limits are reached with increased failure rates
Solution Approach 1:
The patent overcomes horizontal downscaling limits by transitioning to vertical stacking. Memory arrays are extended into the third dimension with multiple substrates stacked together, each containing full-sized memory cells with adequate spacing. This approach continues density improvement without further horizontal miniaturization, thereby avoiding the reliability degradation associated with aggressive downscaling.
4Area of stationary object
If sense amplifier region is separated from memory array on the same substrate, then the memory array area is maximized, but the die size increases and integration density decreases
Solution Approach 1:
The patent places sense amplifier regions on the same vertical level as memory arrays by stacking substrates. Each substrate contains both memory array cells and sense amplifier circuits in the same planar layer, with through-substrate vias providing vertical interconnects. This 3D integration allows maximum memory array area on each substrate while keeping the overall die footprint compact, thereby maintaining high integration density.
Data Source
AI summary
A memory includes at least one first substrate on which unit memory arrays are disposed as a matrix type, each unit memory array including unit memory cells disposed in an array, a second substrate stacked with the at least one first substrate, the second substrate including a sense amplifier region in which sense amplifiers configured to sense information stored in the unit memory cells are disposed, and a plurality of vertical conduction traces configured to electrically connect the at least one first substrate with the second substrate. The sense amplifier region is disposed in a memory region of the second substrate, wherein the memory region of the second substrate corresponds to the memory region of the first substrate.