Stacked DRAM Internal Voltage Output Switching for Chip Testing

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Solution Overview

Problem

The stacking of dynamic random access memory chips in a DRAM IC makes it difficult to measure internal voltages, complicating chip testing.

Innovation Solution

A memory device with a master and slave memory chip configuration, utilizing switching circuits and control circuits to alternately enable and disable internal voltage output from each chip through a shared output pad, allowing for independent measurement of internal voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple memory chips are stacked through TSV to increase capacity, then storage capacity is improved, but internal voltage measurement becomes difficult

Engineering Contradiction:
Improvestorage capacityVSAvoidinternal voltage measurement
Core Design Contradiction:
Quantity of substanceVSDifficulty of detecting and measuring

Solution Approach 1:

The patent divides the stacked memory chip system into master and slave segments, with each chip equipped with independent switching circuits. This segmentation allows individual chips to be tested separately by controlling their respective switching circuits, resolving the measurement difficulty caused by stacking.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces switching circuits as intermediary components between the internal voltage sources and external measurement points. These switching circuits act as mediators that enable selective connection of individual chip voltages to measurement equipment, solving the problem of inaccessible internal voltages in stacked chips.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Difficulty of detecting and measuring

If switching circuits are added to enable individual voltage measurement, then measurement capability is improved, but device complexity increases

Engineering Contradiction:
Improvevoltage measurement capabilityVSAvoidswitching circuit complexity
Core Design Contradiction:
Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The switching circuits are designed with universal functionality to handle both normal operation and measurement modes. The same switching circuit infrastructure serves dual purposes: managing internal voltage distribution during operation and enabling measurement during testing, thereby reducing overall system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent utilizes parameter changes in control signals to switch between measurement and operation modes. By changing the state of switching circuits through control signal parameters, the system achieves measurement capability without requiring separate dedicated measurement hardware, thus minimizing complexity increase.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12609177B2Memory device and internal voltage measuring method thereof
Publication Date: 2026.04.21 NAN YA TECH
  • US12609177B2 patent drawing
  • US12609177B2 patent drawing
  • US12609177B2 patent drawing

AI summary

A memory device and an internal voltage measuring method thereof are provided. Output pads of a master memory chip and a slave memory chip are coupled. When one of a switching circuit of the master memory chip and a switching circuit of the slave memory chip is turned on, the other of the switching circuit of the master memory chip and the switching circuit of the slave memory chip is turned off.