Stacked DSRD Diode Side Passivation for High Breakdown Voltage
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Solution Overview
Problem
Existing methods for manufacturing power semiconductor diodes for pulsed mode operation face challenges in achieving high breakdown voltages due to limitations in diode design and manufacturing processes, particularly in side termination and passivation, which lead to reduced reliability and efficiency.
Innovation Solution
A novel process flow for manufacturing stacked silicon drift step recovery diodes (DSRDs) that integrates improved side termination and passivation methods, including epitaxial growth of graded layers, V-groove etching, thermal oxidation, and selective electroplating, to enhance breakdown voltage and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional soldering and edge sealing methods are used for diode stacking, then assembly is simplified, but breakdown voltage is reduced due to excess solder causing electric shorts and non-uniform current flow
Solution Approach 1:
The patent removes the soldering step entirely from the stacking process. Instead of using solder to bond diodes, the invention employs direct mechanical stacking with edge sealing using silicone compound only for environmental protection, eliminating the harmful effects of excess solder on breakdown voltage
Solution Approach 2:
The patent introduces a new intermediary material system: a specialized adhesive compound replaces solder for bonding diodes in the stack. This adhesive provides both mechanical bonding and electrical isolation functions, preventing electric shorts while maintaining assembly simplicity
2Reliability
If thermal oxidation is used for passivation, then surface passivation is improved, but the process cannot be applied due to existing metal contacts preventing heating above 750°C
Solution Approach 1:
The patent performs thermal oxidation passivation at an early stage in the manufacturing process, before metal contacts are applied to the diode surfaces. By conducting the high-temperature oxidation treatment beforehand, the process achieves excellent surface passivation while avoiding the conflict with subsequent metal contact deposition
Solution Approach 2:
The manufacturing process is divided into distinct stages: first performing thermal oxidation passivation on the silicon surfaces, then applying metal contacts in subsequent steps. This segmentation allows each process to be optimized independently without interference
3Reliability
If depletion zone width is increased to withstand high voltage, then breakdown voltage is improved, but diode area is reduced and side wall effects become more significant
Solution Approach 1:
The patent applies different properties to different regions of the diode: the bulk depletion zone is optimized for voltage withmination, while the side surfaces receive specialized passivation treatment. This local quality approach allows the bulk area to be minimized for voltage handling while the perimeter is enhanced for electrical stability
Solution Approach 2:
The patent uses composite material structures: silicon dioxide passivation layers combined with silicon nitride layers on the diode periphery. This composite approach provides both electrical isolation and mechanical protection, allowing thinner depletion zones without compromising breakdown voltage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method achieves breakdown voltages close to the silicon bulk theoretical limit, improving the reliability and efficiency of DSRD stacks by effectively addressing the limitations of traditional manufacturing processes.
Implementation Method 1
epitaxial grow of graded n and p layers over heavy doped wafer to form wafer size diode structure
Implementation Method 2
etching V-grooves by anisotropic etch through a mask to define side termination surfaces of individual diodes
Implementation Method 3
passivate the silicon surfaces by thermal oxidation
Implementation Method 4
selective electroplating of high melting point metal over the opened silicon surfaces on top of wafer
Data Source
AI summary
Process flow for a stacked power diode and design of the resulting diode is disclosed. Blanket epitaxy over heavy doped wafers is performed. By controlling dopant addition during epitaxy, desired n-type, diode base, and p-type doping profiles and thicknesses achieved. V-groove pattern if formed on wafers by depositing mask film, lithography and anisotropic etch. Islands surrounded by V-grooves define individual diodes. V-grooves serve as side insulation. Next, oxidation step passivates V-grooves. Further, the mask film is stripped to open diode contact areas on both sides of wafers. Next high melting point metal and low melting point metal films are selectively electroplated on all open silicon surfaces. Stacking is performed on wafer level by bonding of desired wafer count by solid-liquid interdiffusion process. Wafer stacks are sawed into individual stacked diode dies along outer slopes of V-grooves. Final stacked devices can be used as DSRD—drift step recovery diodes. Compared to DSRDs made by known methods, better fabrication yield and higher pulse power electrical performance is achieved.