Stacked Deep Trench Capacitor Layout With TSV for Lower ESR

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Solution Overview

Problem

The existing deep trench capacitor (DTC) manufacturing methods are complex and costly, requiring two separate wafers and resulting in a large equivalent series resistance due to the distance between the DTC structure and the die, which affects the voltage stability of integrated circuits.

Innovation Solution

A new method forms a layer of upper and lower trenches within a single wafer, using a through-substrate via (TSV) to connect the die to the DTC structure, reducing the distance and embedding the DTC within the die, thereby simplifying the process and reducing equivalent series resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If two separate wafers are used to form DTC structure, then the DTC structure can be formed with sufficient capacitance, but the equivalent series resistance increases due to the large distance between DTC structure and die

Engineering Contradiction:
Improvevoltage stabilityVSAvoiddistance between DTC structure and die
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent merges the DTC structure formation process into a single wafer, integrating the capacitor formation with the die fabrication. This eliminates the need for separate wafer bonding and reduces the physical distance between the DTC structure and the die, thereby reducing equivalent series resistance and improving voltage stability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent utilizes the vertical dimension by forming trenches that extend through or near the die substrate, allowing the DTC structure to be positioned much closer to the die in the vertical direction rather than requiring lateral proximity, thus reducing the effective distance and associated resistance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If two separate wafers are used for DTC structure, then capacitance can be achieved, but the manufacturing process becomes complex and costly with multiple thin-down processes

Engineering Contradiction:
ImprovecapacitanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the DTC structure formation with the die fabrication process by forming trenches and depositing capacitor structures within the same wafer that contains the die. This integration eliminates multiple separate processing steps including wafer bonding and multiple thin-down processes, thereby reducing manufacturing complexity and cost while maintaining the required capacitance.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single wafer serves multiple functions: it contains both the die and the DTC structure, eliminating the need for separate carrier wafers. This multi-functional approach simplifies the overall manufacturing process by reducing the number of components and processing steps required.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Shape

If two separate wafers are bonded together, then stacked DTC structure can be formed, but the process requires multiple thin-down processes which are costly

Engineering Contradiction:
Improvestacked DTC structureVSAvoidthin-down process cost
Core Design Contradiction:
ShapeVSEase of manufacture

Solution Approach 1:

The patent merges the formation of stacked DTC structures with the die substrate itself, eliminating the need for separate carrier wafers and the associated bonding and thin-down processes. The trenches are formed directly in the die substrate, and the capacitor structures are deposited in place, reducing manufacturing steps and costs.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent extracts the carrier wafer from the process entirely by forming the DTC structure directly in the die substrate. This eliminates the need for wafer bonding and the subsequent thin-down processes required when using separate carrier wafers, thereby reducing manufacturing complexity and cost.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11869988B2Double-sided stacked DTC structure
Publication Date: 2024.01.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11869988B2 patent drawing
  • US11869988B2 patent drawing
  • US11869988B2 patent drawing

AI summary

In some embodiments, the present disclosure relates to an integrated circuit (IC), including a first insulating layer which includes a first metal interconnect structure stacked above a bottom die. Including a substrate disposed above the first insulating layer, a second metal interconnect structure disposed above the substrate, a through-substrate via (TSV) directly connecting the first metal interconnect structure to the second metal interconnect structure, and a stacked deep trench capacitor (DTC) structure disposed in the substrate. The DTC structure includes a first plurality of trenches extending from a first side of the substrate and a second plurality of trenches extending from a second side of the substrate.