Stacked Deep Trench Capacitor Layout With TSV-Coupled Single-Wafer Integration
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Solution Overview
Problem
The existing methods for manufacturing deep trench capacitors (DTCs) are complex and expensive, requiring two separate wafers that are bonded together, leading to increased equivalent series resistance and reduced voltage stability due to the distance between the DTC structure and the die, which exceeds 600 um.
Innovation Solution
A new manufacturing method forms a layer of upper and lower trenches within a single wafer, using a through-substrate via (TSV) to connect the die directly to the DTC structure, reducing the distance to less than 30 um and eliminating the need for a package substrate, thus lowering costs and improving voltage stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two separate wafers are bonded together to form DTC structure, then the DTC structure can be formed with sufficient capacitance, but the distance between DTC structure and die exceeds 600 um leading to increased equivalent series resistance and reduced voltage stability
Solution Approach 1:
The patent merges the formation of upper and lower trenches into a single wafer structure, eliminating the need for bonding two separate wafers. This integration reduces the distance between the DTC structure and die from over 600 um to less than 30 um, thereby reducing equivalent series resistance and improving voltage stability while maintaining the required capacitance.
Solution Approach 2:
The patent utilizes the vertical dimension within a single wafer to stack upper and lower trenches, creating a three-dimensional DTC structure. This vertical stacking approach allows the DTC structure to be positioned much closer to the die in the vertical direction without requiring lateral expansion or wafer bonding, thus reducing the effective distance and improving electrical performance.
2Reliability
If two separate wafers are bonded together to form DTC structure, then the DTC structure can be formed, but the manufacturing process becomes complex and expensive
Solution Approach 1:
The patent combines the formation of both upper and lower trenches within a single wafer processing sequence, eliminating the need for separate wafer fabrication and bonding steps. This merging of processes simplifies the manufacturing workflow, reduces process complexity, and lowers production costs while still achieving the required DTC structure with adequate capacitance.
Solution Approach 2:
The patent extracts and eliminates the unnecessary intermediate step of bonding two separate wafers together. By directly forming both sets of trenches in one wafer, the complex bonding process and associated alignment, cleaning, and verification steps are removed, significantly simplifying the overall manufacturing process.
3Reliability
If two separate wafers are bonded together to form DTC structure, then the DTC structure can be formed, but equivalent series resistance increases due to the large distance between DTC structure and die
Solution Approach 1:
The patent merges the upper and lower trench formations into a single wafer, positioning the DTC structure much closer to the die. This reduction in distance from over 600 um to less than 30 um directly decreases the equivalent series resistance, reducing energy loss in the capacitor structure while maintaining the required capacitance value.
Solution Approach 2:
The patent exploits the vertical stacking capability within a single wafer to position the DTC structure in close proximity to the die in the vertical dimension. This three-dimensional arrangement minimizes the effective electrical path length and reduces equivalent series resistance without requiring lateral expansion or complex inter-wafer connections.
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated circuit (IC), including a first insulating layer which includes a first metal interconnect structure stacked above a bottom die. Including a substrate disposed above the first insulating layer, a second metal interconnect structure disposed above the substrate, a through-substrate via (TSV) directly connecting the first metal interconnect structure to the second metal interconnect structure, and a stacked deep trench capacitor (DTC) structure disposed in the substrate. The DTC structure includes a first plurality of trenches extending from a first side of the substrate and a second plurality of trenches extending from a second side of the substrate.