Stacked Dual Chip Package Leveling Projections
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Solution Overview
Problem
Current DC to DC converter packages are larger than desired due to the side-by-side mounting of high-side and low-side FETs, which increases the footprint and makes them less compact.
Innovation Solution
A lead frame package design featuring a first semiconductor die with a clip structure and leveling projections, where the clip structure is parallel to the die, and an adhesive material is used to attach the clip structure to the die, allowing for a stacked configuration of FETs that reduces the overall package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple FETs are mounted side-by-side in a common package, then electrical connectivity between FETs is achieved, but the package footprint becomes larger than desired
Solution Approach 1:
The patent transitions from a planar side-by-side arrangement of FETs to a three-dimensional stacked configuration. The first and second FETs are positioned at different vertical levels, with the first FET mounted on the lead frame and the second FET mounted on a support structure above it. This vertical stacking enables electrical connectivity between FETs while dramatically reducing the horizontal package footprint, directly resolving the contradiction between maintaining connectivity and minimizing package area.
2Area of stationary object
If FETs are stacked vertically to reduce package size, then package footprint is reduced, but mechanical stability and parallel alignment become challenging
Solution Approach 1:
The patent introduces several intermediary structures to ensure mechanical stability in the stacked configuration. A support structure with leveling projections provides a stable base for mounting the second FET, while an adhesive layer bonds the support structure to the lead frame. These intermediary elements distribute mechanical stresses and maintain precise parallel alignment between the stacked FETs, resolving the stability challenges inherent in vertical stacking while preserving the reduced footprint benefit.
3Area of stationary object
If FETs are stacked vertically to reduce package size, then package footprint is reduced, but achieving parallel alignment between clip structure and die becomes difficult
Solution Approach 1:
The patent incorporates leveling projections on the support structure that extend toward the first FET before the adhesive is applied. These pre-positioned projections establish the correct parallel alignment and spacing between the clip structure and the die in advance of the bonding process. This preliminary action ensures that when the adhesive is applied and cured, the parallel alignment is already established, making the manufacturing process more precise and repeatable while maintaining the compact stacked geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a more compact DC to DC converter package by allowing for the efficient stacking of FETs, reducing the package size while maintaining electrical connectivity, and ensuring stability and even mounting of the semiconductor dies.
Implementation Method 1
an adhesive material is located between at least some of the leveling projections, attaching the clip structure to the first semiconductor die
Data Source
AI summary
The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.