Stacked Dual-DRAM Memory Architecture for Capacity and Bandwidth
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Solution Overview
Problem
The design of dynamic random access memory (DRAM) faces a challenge in balancing high density, high bandwidth, and low power consumption, as improvements in one area often compromise the others, making it difficult to achieve ideal performance and energy efficiency in electronic systems.
Innovation Solution
A memory system incorporating two types of DRAM, one optimized for high density and capacity and the other for low latency and high bandwidth, which are integrated on separate circuits and coupled through a shared physical layer circuit, allowing for efficient energy use and scalable packaging configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM is optimized for high density, then capacity increases, but bandwidth decreases
Solution Approach 1:
The memory system is segmented into two distinct types of DRAM: high-density DRAM for capacity and low-density high-bandwidth DRAM for performance. This segmentation allows each memory type to be optimized independently for its specific function, resolving the contradiction between capacity and bandwidth by distributing different workloads to appropriate memory segments.
2Productivity
If DRAM is optimized for high bandwidth, then latency decreases, but density decreases
Solution Approach 1:
The memory system is segmented into two distinct types of DRAM: high-density DRAM for capacity and low-density high-bandwidth DRAM for performance. This segmentation allows each memory type to be optimized independently for its specific function, resolving the contradiction between capacity and bandwidth by distributing different workloads to appropriate memory segments.
3Quantity of substance
If DRAM density is increased, then capacity increases, but energy efficiency decreases
Solution Approach 1:
The memory system is segmented into two distinct types of DRAM: high-density DRAM for capacity and low-density high-bandwidth DRAM for performance. This segmentation allows each memory type to be optimized independently for its specific function, resolving the contradiction between capacity and bandwidth by distributing different workloads to appropriate memory segments.
Solution Approach 2:
Different DRAM architectures and parameters are used for each memory type to optimize for their specific functions. The high-density DRAM uses parameters optimized for capacity while the low-density high-bandwidth DRAM uses parameters optimized for performance and energy efficiency during active operations.
Data Source
AI summary
In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g., an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.