Stacked Dual-DRAM Memory with Shared PHY for Capacity-Bandwidth Tradeoffs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing DRAM designs face challenges in achieving high bandwidth, high capacity, and low power consumption simultaneously, as design choices that improve one aspect often compromise on the others, making it difficult to create energy-efficient memory systems suitable for portable devices.
Innovation Solution
A memory system comprising two types of DRAM integrated circuits, one optimized for high density and capacity, and the other for low latency and high bandwidth, with a shared physical layer circuit and separate memory controllers, allowing for independent control and optimization of each type to achieve high energy efficiency, high capacity, and low latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM is optimized for high density, then capacity is improved, but bandwidth is reduced
Solution Approach 1:
The memory system is divided into two distinct DRAM types: high-density DRAM for capacity and low-density high-bandwidth DRAM for speed. This segmentation allows each memory type to be independently optimized for its specific function, resolving the contradiction between capacity and bandwidth by providing both specialized memory resources within the same system.
2Productivity
If DRAM is optimized for high bandwidth, then latency is reduced, but capacity is reduced
Solution Approach 1:
The system segments memory functionality into two specialized DRAM types, allowing the low-density high-bandwidth DRAM to provide fast access for frequently used data while the high-density DRAM provides bulk storage capacity. This resolves the bandwidth-capacity contradiction by providing both specialized memory resources.
3Use of energy by moving object
If DRAM is optimized for high capacity, then energy efficiency is improved, but bandwidth is reduced
Solution Approach 1:
The memory system segments storage and bandwidth functions into separate DRAM types. The high-density DRAM provides energy-efficient bulk storage, while the low-density high-bandwidth DRAM handles high-speed data transfer. This segmentation resolves the energy efficiency-bandwidth contradiction by providing specialized memory resources for each function.
4Productivity
If DRAM is optimized for low latency, then bandwidth is improved, but energy efficiency is reduced
Solution Approach 1:
The system segments memory into high-density energy-efficient DRAM and low-density low-latency high-bandwidth DRAM. The low-latency DRAM is used for frequent access operations where speed is critical, while the high-density DRAM handles bulk storage with energy efficiency as the priority. This segmentation resolves the latency-energy efficiency contradiction by providing specialized memory resources.
Data Source
Figure 1~3
Figure 4~7
Figure 8~9
AI summary
In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type maybe a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type maybe on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g. an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.