Stacked Dual MOSFET Package Reduces Interconnection Inductance
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Solution Overview
Problem
Existing power semiconductor packages face inefficiencies due to lead and interconnection inductances, which cause ringing and slow switching speeds, especially in circuits like synchronous buck converters and inverters, where dual MOSFETs operate in complementary fashion, and prior art solutions have not effectively minimized these issues.
Innovation Solution
A stacked dual MOSFET package is designed with a source of the high side MOSFET internally shorted to the drain of the low side MOSFET at a phase node, using conductive tabs and leads to minimize inductances, allowing for zero inductance connections and improved switching efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If MOSFETs are connected with traditional lead and wire interconnections, then the package structure is simple to manufacture, but lead and interconnection inductances cause ringing and slow switching speeds
Solution Approach 1:
The patent transitions from a planar side-by-side MOSFET arrangement to a three-dimensional stacked configuration. The first and second MOSFETs are positioned vertically one above the other, with their respective source and drain regions aligned in the vertical dimension. This spatial reconfiguration dramatically shortens the current path length, minimizing lead and interconnection inductances, thereby reducing ringing and switching losses while improving switching speed.
Solution Approach 2:
The patent merges the source and drain connections of the two MOSFETs by aligning and connecting corresponding regions vertically. The source of the first MOSFET is connected to the drain of the second MOSFET, and the drain of the first MOSFET is connected to the source of the second MOSFET, creating integrated current paths that eliminate separate lead connections and reduce overall inductance.
2Loss of energy
If MOSFETs are co-packaged side by side with wire connections, then some external trace inductances are avoided, but internal wire inductances and complex interconnections remain
Solution Approach 1:
The patent eliminates the need for lateral wire connections by stacking MOSFETs vertically. The current flows directly through vertically aligned source and drain regions within the semiconductor substrate, replacing complex wire and trace interconnections with minimal internal vertical paths. This dimensional change simplifies the interconnection structure while minimizing inductance.
Solution Approach 2:
The patent extracts and eliminates the wire bonding and trace interconnection layers from the package structure. By forming direct vertical connections between stacked MOSFET regions within the substrate, the design removes the intermediate connection elements (wires and traces) that contribute to inductance and complexity, achieving a more direct and simpler current path.
3Productivity
If traditional separate packaging is used for high side and low side MOSFETs, then manufacturing is straightforward, but lead inductances and trace inductances slow down switching and cause losses
Solution Approach 1:
The patent enables higher switching frequencies by stacking MOSFETs vertically, which minimizes the length of current paths and reduces lead and interconnection inductances. The vertical alignment of source and drain regions creates extremely short internal connection paths, allowing faster current transitions and supporting higher switching frequencies with reduced energy losses from inductance.
Data Source
AI summary
A method of fabricating a stacked dual MOSFET die package is disclosed. The method includes the steps of (a) forming a first conductive tab, (b) stacking a high side MOSFET die on the first conductive tab such that a drain contact of the high side MOSFET die is coupled to the first conductive tab, (c) stacking a second conductive tab in overlaying relationship to the high side MOSFET die such that a source contact of the high side MOSFET die is coupled to the second conductive tab, and (d) stacking a low side MOSFET die on the second conductive tab such that a drain contact of the low side MOSFET die is coupled to the second conductive tab.