Stacked Dual-Transistor Memory Cell Design for Dummy Cell Elimination
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Solution Overview
Problem
Conventional electronic devices with single-transistor data cells require dummy cells for comparison, increasing cost and reducing memory capacity due to space consumption, while multi-transistor data cells are not used due to their larger size.
Innovation Solution
The development of a space-efficient dual-transistor data cell design with stacked transistors, allowing for selective disabling of rows or columns to serve as a reference, reducing the need for dummy cells and optimizing memory capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single-transistor data cells are used, then device complexity is reduced, but memory capacity is reduced due to space consumption by dummy cells
Solution Approach 1:
The patent makes data cells multi-functional by enabling them to serve both as storage units and as reference cells through the selective disabling mechanism. The dual-transistor configuration allows each cell to operate in multiple modes (active storage or disabled reference), eliminating the need for separate dummy cells and thereby increasing effective memory capacity while maintaining operational simplicity
Solution Approach 2:
The patent extracts the reference function from dedicated dummy cells and integrates it into the regular data cell array through selective disabling. By removing the requirement for separate dummy cells and incorporating reference functionality within the existing cell structure, the design increases memory capacity without adding device complexity
2Quantity of substance
If multi-transistor data cells are used, then memory capacity is increased, but device area is increased
Solution Approach 1:
The patent transitions from a planar single-transistor layout to a three-dimensional stacked transistor configuration. By stacking transistors vertically, the design achieves higher memory capacity per unit area, effectively resolving the contradiction between increased memory capacity and increased surface area through vertical integration
3Measurement precision
If dummy cells are included for comparison, then measurement precision is improved, but device area is increased
Solution Approach 1:
The patent makes data cells multi-functional by enabling them to serve both as storage units and as reference cells through the selective disabling mechanism. The dual-transistor configuration allows each cell to operate in multiple modes (active storage or disabled reference), eliminating the need for separate dummy cells and thereby increasing effective memory capacity while maintaining operational simplicity
Solution Approach 2:
The patent extracts the reference function from dedicated dummy cells and integrates it into the regular data cell array through selective disabling. By removing the requirement for separate dummy cells and incorporating reference functionality within the existing cell structure, the design increases memory capacity without adding device complexity
Data Source
AI summary
A device may include a first transistor, a second transistor, and a data element. The first transistor may have a column gate and a channel, and the second transistor may include a row gate that crosses over the column gate, under the column gate, or both. The second transistor may also include another channel, a source disposed near a distal end of a first leg, and a drain disposed near a distal end of a second leg. The column gate may extend between the first leg and the second leg. The channel of the second transistor may be connected to the channel of the first transistor, and the data element may be connected to the source or the drain. Methods, systems, and other devices are contemplated.