Stacked eFuse Memory Circuits for High-Voltage Programming Stress

The bit-cell is divided into multiple stacked transistors (first transistor, second transistor, third transistor) arranged in series between the efuse element and ground. This segmentation distributes the high voltage stress across multiple devices rather than concentrating it on a single power switch, enabling programming capability while improving device reliability.

The patent transitions from a planar single-transistor configuration to a vertical stacking architecture. By arranging transistors in the vertical dimension (stacked in series), the design achieves both high voltage programming capability and reduced voltage stress through distributed architecture, resolving the reliability contradiction.

The stacked transistor circuit serves multiple functions: it acts as the bit-cell switching element, provides voltage stress distribution, and integrates with peripheral circuits (sense amplifier, power switch) that also use stacking. This multi-functionality achieves high integration density while managing complexity through standardized stacking architecture.

The patent merges the bit-cell transistor stack with peripheral circuit transistors into a unified stacked architecture. By combining multiple functional blocks (bit-cell, sense amplifier, power management) into a consistent stacking style, the design achieves high integration density while controlling overall system complexity through architectural uniformity.