Stacked EIC-PIC Packaging to Reduce Wiring Voltage Drop
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Solution Overview
Problem
Existing photonic computing systems face issues with excessive voltage drop due to long wirings between electronic and photonic integrated circuit chips, leading to power consumption and integration limitations, especially when multiple connection points and optical coupling are involved.
Innovation Solution
A semiconductor device design where the electronic integrated circuit chip is positioned between the photonic integrated circuit chip and the substrate, utilizing a rewiring structure and via conductive paths to reduce wiring distance, including redistribution metal layers and via conductive structures to optimize electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If long wirings are used to connect EIC chip and PIC chip, then electrical connection is achieved, but voltage drop increases and power consumption increases
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional vertical wiring by stacking the EIC chip above the PIC chip. This dimensional change allows electrical connections to be made through vertical vias and conductive structures rather than long horizontal traces, significantly reducing the wiring length and associated voltage drop while maintaining reliable electrical connection.
Solution Approach 2:
The patent divides the electrical connection path into multiple segmented components including via structures, conductive layers, and bonding interfaces. This segmentation allows each component to be optimized independently for minimal resistance and optimal connection, reducing overall voltage drop across the EIC-PIC interface.
2Productivity
If multiple connection points and wirings are used for data transmission, then data transmission capability is improved, but voltage drop increases
Solution Approach 1:
The patent utilizes multiple vertical via structures arranged in a three-dimensional configuration to establish multiple parallel electrical connection paths between EIC and PIC. This vertical multi-path architecture enables high-capacity data transmission while keeping each individual wiring path short, thereby maintaining low voltage drop despite multiple connection points.
Solution Approach 2:
The patent segments the data transmission function across multiple parallel via structures and conductive paths. Each segment handles a portion of the data transmission load, and the parallel arrangement reduces the current burden on each individual path, minimizing voltage drop while achieving high overall data transmission capability.
3Adaptability or versatility
If PIC chip is optically coupled with external devices, then optical functionality is achieved, but integration is limited
Solution Approach 1:
The patent merges the optical coupling function directly into the stacked EIC-PIC architecture by integrating optical interfaces at the chip levels. This combination eliminates the need for separate external optical coupling components, achieving full optical functionality while maintaining a compact, highly integrated device structure.
Solution Approach 2:
The patent implements optical coupling in the vertical dimension through the stacked chip architecture, allowing optical interfaces to be positioned at different heights and orientations. This three-dimensional optical integration enables versatile external device coupling without increasing planar footprint or compromising integration density.
Data Source
AI summary
The present invention relates to the field of photonic integrated circuits and provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes an EIC chip and a PIC chip arranged on a substrate, the EIC chip is located between the PIC chip and the substrate. In embodiments, at least one EIC chip is disposed on a surface of a single PIC chip facing the substrate, and the EIC chip is mounted on the substrate through a connection structure. Therefore, the wiring of the PIC chip in the semiconductor device of the present invention is optimized such that the voltage drop due to long wiring distance can be suppressed, and the package structure of the semiconductor device is also optimized.