Stacked Electrode Thin Film Transistor for High-Density Display Patterning
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Solution Overview
Problem
High-precision display technologies, such as 8K displays, require high wire arrangement density, leading to signal crosstalk and short circuits due to dimensional errors in thick wire formation, which increases resistance and affects signal transmission speed.
Innovation Solution
A thin film transistor design with stacked electrodes and a semiconductor layer, where at least one of the electrodes comprises multiple portions stacked in direct contact, reducing the thickness of each portion in the patterning process to minimize dimensional errors and improve etching accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the wire thickness is increased to reduce resistance and increase signal transmission speed, then the electrical conductivity improves, but the manufacturing precision deteriorates due to large dimensional errors in thick wire formation
Solution Approach 1:
The patent divides the thick wire structure into multiple thin film layers stacked together. Each layer has controllable thickness within the precise patterning range, while the cumulative thickness of multiple layers achieves the desired total wire thickness for low resistance. This segmentation allows the wire to simultaneously achieve both low resistance (through sufficient total thickness) and high manufacturing precision (through controlled thin layer deposition).
2Area of stationary object
If the wire arrangement density is increased to meet high-precision display requirements, then the area utilization improves, but the reliability deteriorates due to signal crosstalk and short circuits between adjacent wires
Solution Approach 1:
The patent transitions from planar wire arrangement to three-dimensional stacked wire structures. Multiple wire layers are stacked vertically with insulating layers between them, enabling high wire density in the horizontal plane while maintaining electrical isolation through the vertical dimension. This dimensional transition allows adjacent wires to be closely spaced without causing crosstalk or short circuits, as the insulating layers provide effective electrical separation.
3Reliability
If the wire thickness is increased to reduce resistance, then the electrical conductivity improves, but the manufacturing complexity increases due to difficulty in achieving precise patterning of thick films
Solution Approach 1:
The patent segments the thick wire formation process into multiple thin film deposition and patterning steps. Each thin layer can be precisely patterned using standard photolithography and etching processes, avoiding the difficulties of patterning thick films in a single step. The stacked layers are formed sequentially, with each layer being independently patterned and controlled, thereby simplifying the overall manufacturing process while achieving the desired total wire thickness for low resistance.
Data Source
AI summary
A thin film transistor and a manufacture method thereof, an array substrate and a manufacture method thereof are provided. The manufacture method of the thin film transistor includes: providing a base substrate; and forming a gate electrode, a first electrode, a second electrode and a semiconductor layer of the thin film transistor on the base substrate. At least one of the gate electrode, the first electrode and the second electrode includes N portions that are stacked in a direction perpendicular to the base substrate, adjacent two of the N portions are in direct contact with each other, and N is a positive integer more than or equal to 2. The method includes: performing N patterning processes to respectively form the N portions.