Stacked Electronics Package With Multi-Thickness Conductor Layers
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Solution Overview
Problem
Existing electronics packaging technologies face challenges in miniaturization, design flexibility, and cost efficiency due to the substantial thickness of prior art arrangements, which limit product miniaturization and weaken electrical performance, especially in high-performance applications.
Innovation Solution
An electronics package is designed with a stacked configuration of electrical components on an insulating substrate, featuring a multi-thickness conductor layer with varying routing density and current carrying capabilities, allowing for closer integration of disparate components and reduced conductor length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If individually packaged components are mounted on a multi-layer PCB with substantial thickness, then each component can be separately packaged and connected, but the overall package thickness increases and product miniaturization is limited
Solution Approach 1:
The patent transitions from planar mounting of individually packaged components on a PCB to a three-dimensional stacked configuration where components are vertically arranged above and below a substrate. This dimensional change reduces the horizontal footprint and enables miniaturization while maintaining separate packaging of individual components.
Solution Approach 2:
The patent merges multiple individually packaged components into a single integrated stacked package structure. By combining the substrate, multiple components, and interconnectors into one unified assembly, the overall package thickness is reduced compared to mounting separate components on a thick PCB.
2Adaptability or versatility
If multiple routing layers are used to connect electrical components, then connectivity between components is achieved, but the conductor structure becomes long and complex, weakening electrical performance
Solution Approach 1:
The patent uses vertical interconnectors that extend through the substrate to create direct electrical pathways between components on opposite sides. This three-dimensional routing approach replaces long, complex planar routing paths with shorter vertical conduits, reducing conductor length and improving electrical performance.
Solution Approach 2:
The patent introduces through-substrate interconnectors as intermediary elements that facilitate direct electrical connection between components on opposite sides of the substrate. These interconnectors act as mediators that shorten the electrical path compared to traditional multi-layer PCB routing.
3Ease of manufacture
If conductor layers with uniform thickness are used, then manufacturing is simplified, but routing density and current carrying capabilities cannot be locally optimized for different electronics devices
Solution Approach 1:
The patent implements conductor layers with locally varied thicknesses where different regions have different thicknesses optimized for their specific functions. High current regions have thicker conductor sections while high-density routing regions have appropriately sized conductors, enabling local optimization of both routing density and current carrying capabilities.
Solution Approach 2:
The patent changes the thickness parameter of conductor layers at different locations to optimize performance. By varying the conductor thickness parameter locally rather than maintaining uniform thickness, the design achieves both high routing density in some areas and high current carrying capability in others.
Data Source
AI summary
An electronics package includes an insulating substrate, a first electrical component coupled to a top surface of the insulating substrate, and a second electrical component coupled to a bottom surface of the insulating substrate. A first conductor layer is formed on the bottom surface of the insulating substrate and extends through a via formed therethrough to contact a contact pad of the first electrical component, with a portion of the first conductor layer positioned between the insulating substrate and the second electrical component. A second conductor layer is formed on the top surface of the insulating substrate and extends through another via formed therethrough to electrically couple with the first conductor layer and to contact a contact pad of the second electrical component.