Stacked Fan-Out Chip Packaging with Vertical Through-Hole Interconnects
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Solution Overview
Problem
Traditional semiconductor packaging methods struggle to achieve thinner profiles and higher interconnection densities due to limitations in gold wire height, substrate material constraints, and pad spacing, making it difficult to meet the demands of smaller, more functional electronic products.
Innovation Solution
A fan-out packaging method involving a dummy chip with a groove, where a first chip is fixed within the groove and multiple second chips are bonded and stacked, using conductive through holes for vertical interconnection, and redistribution wiring layers for enhanced connectivity, allowing for reduced package height and higher density interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional wire bonding connection or reverse soldering connection is used, then pad spacing can be maintained above 30 μm, but it is extremely difficult to continue shrinking the pad spacing
Solution Approach 1:
The patent transitions from planar pad spacing reduction to vertical stacking dimension. Multiple chips are stacked vertically with interconnection through conductive through-holes, allowing high interconnection density without further shrinking horizontal pad spacing. The redistribution wiring layer provides additional routing dimensionality.
Solution Approach 2:
The patent implements nested structure where multiple chips are stacked vertically, with conductive through-holes penetrating through chips to connect lower chips to upper chips. This nested vertical arrangement achieves high interconnection density without requiring smaller pad spacing on individual chip layers.
2Length of moving object
If ultra-thin substrate is produced, then package thickness can be reduced, but production is extremely difficult due to limitations of substrate materials and substrate strength
Solution Approach 1:
The patent segments the package into multiple discrete chip layers stacked vertically, each chip maintaining its structural integrity. This eliminates the need for a single ultra-thin substrate, as each chip layer can be manufactured with standard thickness requirements while achieving overall thin package profile through vertical stacking.
Solution Approach 2:
The patent uses composite structure combining multiple chip materials, bonding materials, and encapsulation materials. This composite approach allows each layer to be optimized for its specific function and manufacturing capabilities, avoiding the need for a single ultra-thin substrate material that would need to satisfy all requirements simultaneously.
3Length of moving object
If height from plastic encapsulant to chip surface is reduced, then package can be thinner, but it is strictly limited by limitation of molding height of gold wire and protection distance from plastic encapsulant to gold wire
Solution Approach 1:
The patent extracts and removes the gold wire bonding process entirely, replacing it with direct chip-to-chip bonding through conductive through-holes. This eliminates the need for gold wires and their associated molding height requirements and protection distances, enabling significantly reduced package height.
Solution Approach 2:
The patent replaces the mechanical gold wire bonding system with a direct electrical and mechanical connection system using conductive through-holes and redistribution wiring layers. This substitution eliminates the need for wire bonding infrastructure and associated spatial requirements.
4Quantity of substance
If interconnection density is increased, then more functions can be integrated, but traditional packaging cannot meet future demands for higher density
Solution Approach 1:
The patent adds the vertical stacking dimension to achieve high interconnection density. Multiple chips are connected through conductive through-holes in a vertical arrangement, providing extensive interconnection capacity without increasing horizontal pad density. The redistribution wiring layer further multiplies connection possibilities.
Solution Approach 2:
The conductive through-holes serve multiple functions: providing electrical interconnection between chips, enabling mechanical bonding, and facilitating thermal management. The redistribution wiring layer provides both signal routing and structural support, achieving multi-functionality that enhances interconnection density and adaptability.
Data Source
AI summary
A fan-out packaging method and packaging structure are provided. The method includes: fixing a first chip in a groove of a dummy chip; bonding a plurality of second chips with the dummy chip and the first chip respectively; forming a first plastic encapsulation layer to wrap the plurality of second chips; forming a second plastic encapsulation layer to wrap the first chip, the dummy chip, and the first plastic encapsulation layer; and forming a redistribution wiring layer on surfaces of the dummy chip and the first chip away from the plurality of second chip.