Stacked Ferroelectric RAM Capacitors for Multi-State Memory Density
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Solution Overview
Problem
Conventional binary ferroelectric RAM (FRAM) devices have limited storage states and programming flexibility, and there is a need for a more efficient and non-volatile memory solution that can occupy a smaller footprint on a chip.
Innovation Solution
A multi-state ferroelectric-RAM device with vertically stacked capacitors of varying thicknesses, allowing for multiple storage states and shared electrodes to reduce chip footprint, utilizing a method of manufacturing that includes forming ferroelectric capacitors with different thicknesses and isolation layers to prevent parasitic leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional binary FRAM devices are used, then the device structure is simple, but the storage states are limited and programming flexibility is reduced
Solution Approach 1:
The ferroelectric capacitor is segmented into multiple layers with different thicknesses, where each layer can be independently programmed to different resistance states. This segmentation enables multi-state storage while maintaining a relatively simple overall device structure based on the conventional FRAM architecture.
Solution Approach 2:
Different regions of the ferroelectric capacitor have locally varied properties through different thicknesses of ferroelectric material in each layer. This local quality variation allows each layer to contribute differently to the overall resistance state, enabling flexible programming and multiple storage states.
2Adaptability or versatility
If vertically stacked capacitors with varying thicknesses are used, then programming flexibility and storage states are increased, but the device complexity increases
Solution Approach 1:
The invention transitions from a conventional planar capacitor structure to a vertically stacked three-dimensional structure. By adding the vertical dimension with multiple layers of varying thicknesses, the device achieves enhanced programming flexibility and multi-state storage capability while managing the increased manufacturing complexity through systematic layer formation processes.
3Area of stationary object
If shared electrodes are used between adjacent memory cells, then chip footprint is reduced, but parasitic leakage between electrodes may occur
Solution Approach 1:
An isolation layer is introduced as an intermediary element between the shared electrodes of adjacent memory cells. This isolation layer prevents parasitic leakage current while allowing the electrodes to be shared, thereby reducing chip footprint without sacrificing electrical isolation.
4Reliability
If isolation layers are added to prevent parasitic leakage, then electrode isolation is improved, but manufacturing complexity increases
Solution Approach 1:
The isolation layer formation process is merged with the existing capacitor formation工艺流程. The isolation layer is integrated into the vertical stack structure, combining the isolation function with the capacitor structure rather than adding it as a completely separate component, thereby managing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves increased programming flexibility and efficiency, with non-volatile storage and reduced power consumption, making it a viable alternative to flash-based devices.
Implementation Method 1
Vertically stacked ferroelectric capacitors are formed on the substrate. A first ferroelectric capacitor has a different capacitive output than a second ferroelectric capacitor when a constant voltage is applied.
Implementation Method 2
A first capacitor plate in the first ferroelectric capacitor and a second capacitor plate in the second ferroelectric capacitor have different thicknesses. The different thicknesses allow the capacitive output for each capacitor to produce different electric field outputs.
Data Source
AI summary
A memory device includes a substrate and vertically stacked ferroelectric capacitors formed on the substrate. A first ferroelectric capacitor has a different capacitive output than a second ferroelectric capacitor when a constant voltage is applied. First and second electrodes are in electrical contact with the vertically stacked ferroelectric capacitors. In some instances, a first capacitor plate in the first ferroelectric capacitor and a second capacitor plate in the second ferroelectric capacitor have different thicknesses. The different thicknesses allow the capacitive output for each capacitor to produce different electric field outputs. Accordingly, a combination of different output signals can be produced based on different threshold voltage levels for each capacitor contributing to the output.