Vertically Stacked FET Amplifier Layout for Parasitic Capacitance
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Solution Overview
Problem
In amplifier circuits using vertically stacked FETs, parasitic capacitances at via holes between FET elements degrade the circuit's characteristics, particularly as the number of vertical-stacking connections increases.
Innovation Solution
The amplifier circuit incorporates an element isolation portion between adjacent FETs to prevent leakage currents and reduce parasitic capacitances, while a connection portion electrically connects the drain of one FET to the source of another, thereby minimizing the impact of parasitic capacitances on circuit characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If vertically stacking and connecting a plurality of FETs to support high power supply voltages, then pressure resistance is improved, but parasitic capacitances occur at via holes between elements which affect amplifier circuit characteristics
Solution Approach 1:
The patent divides the vertically stacked FET structure into segments with element isolation portions inserted between adjacent FETs. This segmentation approach maintains the voltage division benefit while isolating parasitic capacitance effects to specific regions, preventing them from affecting the entire amplifier circuit characteristics.
Solution Approach 2:
The element isolation portion extracts and removes the harmful parasitic capacitance effect by providing isolation between adjacent FET elements. This allows the beneficial vertical stacking for voltage support to continue while removing the detrimental capacitance coupling between stages.
2Stress or pressure
If increasing the number of vertical-stacking connections to support higher power supply voltages, then withstand voltage capability is improved, but parasitic capacitances due to via holes increase and degrade amplifier circuit characteristics
Solution Approach 1:
By inserting element isolation portions between vertically stacked FETs, the patent segments the high-voltage structure into isolated units. This allows the system to achieve high withstand voltage through multiple stacking levels while preventing parasitic capacitance from degrading amplifier characteristics across the entire structure.
Data Source
AI summary
An amplifier circuit includes a first FET having a gate, a second FET and a third FET that are connected between a power supply and a reference potential along with the first FET, a substrate on which the first, second, and third FETs are formed, the first, second, and third FETs being vertically stacked and connected, respective gates of the first, second, and third FETs being disposed side by side in cross-sectional view of the substrate along a direction in which the first, second, and third FETs are vertically stacked and connected, an element isolation portion configured to isolate from each other two FETs adjacent to each other of the first, second, and third FETs, and a connection portion configured to connect a drain of one of the two FETs and a source of another one of the two FETs.