Stacked FET Backside Angle Cut for Denser Interconnect Routing
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Solution Overview
Problem
In stacked field effect transistors (FETs), the routing space becomes tight when backside contacts need to be wired to both backside and frontside interconnects, complicating the layout and reducing efficiency.
Innovation Solution
The semiconductor structure includes a first stacked FET cell with a second FET stacked over a first FET, a second stacked FET cell adjacent to the first, and angled backside source/drain contact structures that laterally separate the contact regions, allowing for efficient routing and interconnectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If backside contacts are wired to both backside and frontside interconnects, then interconnectivity is achieved, but routing space becomes tight and layout complexity increases
Solution Approach 1:
The patent introduces an angled cut region that creates a three-dimensional separation structure between adjacent backside source/drain contact structures. This angular geometry (e.g., 45 degrees) provides additional spatial dimension for routing, allowing interconnects to pass through the angled region without increasing planar layout complexity, thus resolving the contradiction between achieving interconnectivity and maintaining simple layout
2Adaptability or versatility
If backside contacts are wired to both backside and frontside interconnects, then interconnectivity is achieved, but routing space becomes tight
Solution Approach 1:
The patent segments the backside contact region by introducing angled cut regions that laterally separate adjacent backside source/drain contact structures. This segmentation creates distinct routing corridors for different interconnects, improving routability by providing dedicated pathways while containing the routing complexity within specific angular regions rather than requiring extensive planar space
3Productivity
If angled cut region is introduced to separate contact structures, then routing efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The patent specifies particular angular parameters for the angled cut regions (e.g., 45 degrees) that optimize routing efficiency while maintaining compatibility with standard semiconductor manufacturing processes. By defining specific geometric parameters, the design achieves improved routing efficiency through angular separation while keeping manufacturing complexity manageable through parameter standardization
Data Source
AI summary
A semiconductor structure is provided that includes a first stacked FET cell including a second FET stacked over a first FET, and a second stacked FET cell located adjacent to the first stacked FET cell and including a fourth FET stacked over a third FET. The structure further includes a first backside source/drain contact structure located beneath the first stacked FET cell and contacting a source/drain region of the first FET, a second backside source/drain contact structure located beneath the second stacked FET cell and contacting a source/drain region of the third FET, and an angled cut region laterally separating the first backside source/drain contact structure from the second backside source/drain contact structure.