Stacked FET Backside Contact Layout for Dense SFET Integration
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Solution Overview
Problem
Fabricating stacked field effect transistors (SFETs) at small scales poses challenges in forming contacts between top and bottom transistors, especially when dealing with different gate materials, which requires complex masking to prevent cross-layer effects.
Innovation Solution
The semiconductor device includes a bottom layer with pairs of channel regions separated by dielectric bars, featuring an integral backside contact, and a top layer with channel regions laterally offset from the bottom layer. This configuration allows for the formation of like-typed transistors with narrow spacing and larger spaces between differently typed transistors, enabling the use of large backside gate contacts without penetrating contacts between layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contacts are formed between top and bottom transistors at small scales, then electrical connectivity is achieved, but manufacturing complexity increases due to challenging contact formation processes
Solution Approach 1:
The patent transitions from planar contact formation to three-dimensional contact architecture by forming contacts on the backside of the substrate. This dimensional change allows contacts to be made to the bottom transistor without penetrating through the top transistor, eliminating the need for complex through-silicon via processes and reducing manufacturing complexity while maintaining electrical connectivity.
Solution Approach 2:
The patent segments the contact formation process into separate frontside and backside operations. The bottom transistor contacts are formed on the backside of the substrate, while the top transistor contacts remain on the frontside. This segmentation avoids the need for single-sided complex masking and contact formation, simplifying the overall manufacturing process.
2Adaptability or versatility
If complex masking is used to prevent cross-layer effects during processing, then different gate materials can be fabricated, but device complexity and processing steps increase
Solution Approach 1:
By moving to backside contact formation, the patent creates independent processing zones on the frontside and backside of the substrate. This allows different gate materials to be fabricated on the frontside without requiring complex masking to prevent cross-layer effects, as the backside processing is spatially separated and does not interfere with frontside transistor structures.
Solution Approach 2:
The patent segments the device into frontside transistor regions and backside contact regions, allowing independent processing of each. This segmentation enables versatile gate material fabrication on the frontside while simplifying the processing on the backside, reducing the need for complex cross-layer masking.
3Productivity
If like-typed transistors are spaced closely to increase density, then transistor density improves, but spacing between differently typed transistors may be insufficient
Solution Approach 1:
The patent utilizes the third dimension (substrate thickness) by forming contacts on the backside, which allows like-typed transistors to be spaced closely on the frontside for high density without compromising the spacing requirements for differently typed transistors. The backside contact approach provides additional spatial freedom to optimize frontside transistor layout.
Data Source
AI summary
Semiconductor devices include a bottom layer and a top layer. The bottom layer includes a pair of first channel regions being separated by a first dielectric bar, a pair of second channel regions being separated by a second dielectric bar, and a gate structure having an integral backside contact between the first channel regions and the second channel regions. The top layer includes third channel regions, over and laterally offset with respect to the first channel regions, and fourth channel regions, over and laterally offset with respect to the second channel regions.