Backside Contact Layout for Stacked FET Power Rail Routing
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Solution Overview
Problem
In semiconductor device fabrication, stacked FET structures face challenges in contact wiring layout and potential electrical shorting, necessitating improved routing characteristics for backside power rails and power distribution networks.
Innovation Solution
The method involves forming a first field effect transistor (FET) with a second FET stacked over it, along with a backside contact connected to a backside power rail and a via to backside power rail that lands over the backside contact, optimizing contact wiring structures for enhanced routing and distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked FET structures are implemented to increase device density, then active density is improved, but contact wiring layout complexity increases and electrical shorting risk increases
Solution Approach 1:
The patent introduces backside contacts that extend through the substrate to the back surface of the semiconductor device, utilizing the vertical dimension to route power rails away from the planar contact wiring layer. This dimensional transition allows power distribution to occur in a different spatial plane, eliminating conflicts with front-side contact layouts and reducing wiring complexity despite increased device density.
2Quantity of substance
If stacked FET structures are implemented to increase device density, then active density is improved, but risk of electrical shorting increases
Solution Approach 1:
Power rails are routed through the substrate to the back surface of the device, separating the power distribution path from the front-side contact wiring layer. This spatial separation in the vertical dimension eliminates potential shorting paths between adjacent stacked FET contacts while maintaining high device density.
Solution Approach 2:
The power distribution network is segmented into separate backside power rails that are physically isolated from front-side contacts. This segmentation creates distinct electrical domains, preventing unintended current paths and reducing shorting risk in densely stacked FET configurations.
3Ease of manufacture
If conventional contact wiring is used in stacked FET structures, then manufacturing is simpler, but routing characteristics are insufficient and power distribution efficiency is reduced
Solution Approach 1:
The patent routes power rails through the substrate to the back surface, utilizing the vertical dimension to create dedicated power distribution pathways. This approach maintains manufacturing simplicity by using standard through-substrate via techniques while dramatically improving power distribution efficiency by eliminating routing conflicts and reducing resistance in the power delivery path.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a first field effect transistor (FET); a second FET stacked over the bottom FET; a backside contact (BSCA) connected to a backside power rail (BSPR); and a via to backside power rail (VBPR), the VBPR landing over the BSCA.