Stacked FET Layout With Backside Metal for High-Frequency Response
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Solution Overview
Problem
In field effect transistors (FETs) with finger-shaped electrodes, improving high-frequency characteristics requires appropriate setting of gate resistance, source inductance, and other parameters, but existing configurations face challenges in optimizing these aspects simultaneously.
Innovation Solution
The semiconductor device incorporates a specific arrangement of transistors and metal layers on a substrate, including overlapping source electrodes, interconnected drain electrodes, and strategically placed gate lines, via holes, and back-surface metal layers to reduce gate resistance and source inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple unit FETs are arranged in an extending direction of the electrodes, then the transistor density is improved, but the gate resistance and source inductance increase deteriorating high-frequency characteristics
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked configuration. Unit FETs are arranged in multiple layers vertically, with source electrodes overlapping in the thickness direction. This vertical stacking enables higher transistor density while maintaining short gate and source connection lengths, thereby preserving high-frequency characteristics despite increased integration density.
Solution Approach 2:
The patent implements nested interconnection structures where via holes are formed within overlapping source electrode regions. Multiple via holes are arranged in the thickness direction to create vertical connection paths that pass through stacked FET layers. This nested configuration enables efficient electrical connection between multiple transistor layers while minimizing parasitic inductance and resistance.
2Area of stationary object
If source electrodes of multiple FETs are overlapped to increase density, then the area is reduced, but the source inductance increases affecting high-frequency performance
Solution Approach 1:
The patent utilizes the thickness direction (z-axis) to create vertical connection paths through via holes that penetrate through the overlapping source electrode regions. This three-dimensional interconnection approach allows compact planar layout while maintaining short current paths, thereby reducing source inductance despite the overlapped configuration.
Solution Approach 2:
The patent introduces via holes as intermediary connection structures between the overlapping source electrodes of different FET layers. These via holes provide direct vertical electrical connection paths that bypass the horizontal routing, effectively reducing the source inductance that would otherwise result from the overlapped electrode configuration.
3Adaptability or versatility
If gate lines are extended to connect multiple gate electrodes, then the control capability is improved, but the gate resistance increases reducing high-frequency response
Solution Approach 1:
The patent employs vertical via hole connections to establish gate electrode pathways in the thickness direction. This three-dimensional gate interconnection structure enables comprehensive control of multiple FET layers while maintaining short current paths, thereby achieving both high gate control capability and low gate resistance for improved high-frequency response.
Data Source
AI summary
A semiconductor device includes a substrate having a main surface and a back surface opposite to the main surface, a first transistor disposed on the main surface, a second transistor disposed on the main surface, a third transistor disposed on the main surface between the first transistor and the second transistor, a first gate line disposed on the main surface, and a back-surface metal layer disposed on the back surface.