Stacked FET Backside Wiring Layout With Self-Aligned Isolation
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Solution Overview
Problem
Existing integrated circuit technologies face challenges in achieving compact, high-density, and high-quality semiconductor devices with efficient self-alignment and cost-effective manufacturing, particularly in stacked transistor configurations.
Innovation Solution
A method for forming integrated circuit devices involving the formation of a stack of field effect transistors with self-aligned trenches and holes, allowing for the creation of a backside wiring line that is electrically isolated from source/drain regions, facilitating compact and high-density configurations with reduced misalignment errors and lower manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional planar semiconductor devices are used, then manufacturing is simpler, but area efficiency and power efficiency are reduced
Solution Approach 1:
The patent transitions from traditional planar (2D) semiconductor devices to vertical (3D) stacked transistor devices. Multiple transistor layers are stacked vertically on top of each other, utilizing the third dimension to increase area efficiency while maintaining manageable manufacturing complexity through standardized vertical fabrication processes
2Area of moving object
If stacked transistor devices are used, then area efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements self-aligned fabrication processes where each subsequent layer is automatically positioned relative to previous layers through conformal deposition and etch-stop mechanisms. The vertical stacking process uses the underlying layers as their own alignment references, eliminating the need for separate high-precision alignment steps and reducing manufacturing precision requirements
3Productivity
If higher density configurations are used, then device density improves, but parasitic capacitances increase
Solution Approach 1:
The patent extracts and removes parasitic capacitance sources through carefully designed isolation structures and spacing between closely packed vertical transistor layers. Dielectric materials are strategically placed between stacked layers to eliminate unwanted capacitive coupling, allowing high device density without proportionally increasing parasitic effects
4Manufacturing precision
If self-alignment is implemented, then manufacturing complexity increases, but misalignment errors are reduced
Solution Approach 1:
The self-aligned fabrication process uses the previously formed layers as automatic alignment references for subsequent layers. Each vertical layer is deposited conformally on the previous layer, and etch processes use underlying structures as alignment guides, making the system self-correcting and eliminating the need for complex external alignment systems
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables compact, high-density integrated circuit devices with improved performance and reduced parasitic capacitances, while allowing for flexible production and efficient signal routing designs.
Implementation Method 1
performing a first metal deposition to fill the first hole; the second hole; and at least part of the first trench, with metal
Implementation Method 2
performing a second metal deposition to fill the first trench with metal
Data Source
Figure 1a~1b
Figure 2a~2f
Figure 3~5
AI summary
A method for forming an integrated circuit device (1), the method comprising: forming a stack of field effect transistors (60), FETs, comprising a bottom FET (61) and a top FET (62); forming a first trench (5) underneath the bottom FET (61); forming a first hole (10), between the first trench (5) and a first source/drain region (51) of the bottom FET (61); forming a second hole (20), between the first hole (10) and a contact (81) of a contact layer (80) arranged above the top FET (62); performing a first metal deposition to fill the first hole (10); the second hole (20); and part of the first trench (5), with metal; recessing the metal deposited in the first metal deposition; forming an isolation layer (92) below the recessed metal; performing a second metal deposition to fill the first trench (5) with metal, thereby forming a first backside wiring line (71) in the first trench (5).