Stacked FET Bottom Contact Resistance Reduction
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Solution Overview
Problem
Current field effect transistors face challenges in achieving optimized bottom source/drain contact resistance, which is a bottleneck for device performance improvement.
Innovation Solution
The semiconductor device includes a top field effect device over a bottom field effect device with a bottom contact electrically connecting the bottom source/drain to a buried power rail, and a bottom contact cap on the bottom contact, along with a trench liner on opposite sides, to form a stacked field effect transistor with reduced contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FET structures are used with horizontal current flow, then device fabrication is simpler, but contact resistance cannot be optimized sufficiently
Solution Approach 1:
The patent transitions from conventional horizontal current flow in the substrate plane to vertical current flow through stacked FET structures. The bottom FET's source/drain contacts extend vertically to connect to buried power rails, creating a three-dimensional contact architecture that reduces contact resistance by providing multiple contact paths and larger contact area with the power rail.
Solution Approach 2:
The patent implements a stacked FET configuration where a top FET is positioned directly over a bottom FET, with the bottom FET's source/drain region nested within the structure. The bottom contact extends vertically through the substrate to connect to the buried power rail, creating a nested arrangement where contacts are embedded within the device structure to achieve optimized electrical connection.
2Reliability
If bottom source/drain contact resistance is reduced to improve device performance, then device performance improves, but contact structure becomes more complex
Solution Approach 1:
The patent divides the FET structure into distinct top and bottom FETs with separate gate structures, channel regions, and source/drain regions. The bottom FET's source/drain is segmented into a contact region that extends vertically to the buried power rail, allowing independent optimization of the contact structure without affecting the overall device operation.
Solution Approach 2:
The patent introduces a bottom contact as an intermediary element that extends vertically from the bottom FET's source/drain region to the buried power rail. This intermediary contact structure facilitates optimized electrical connection by providing a dedicated low-resistance path, separating the contact function from the active device region.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a top field effect device over a bottom field effect device, and a bottom contact electrically connecting a bottom source/drain of the bottom field effect device to a first buried power rail. The semiconductor device further includes a bottom contact cap on the bottom contact, and a trench liner on opposite sides of the bottom contact cap and the bottom contact.