Stacked FET Structure for Lower Gate-to-Source/Drain Capacitance
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Solution Overview
Problem
Parasitic capacitance between the gate electrode and the source/drain region in integrated circuit devices, particularly in 3D-stacked FETs, deteriorates the AC performance and is influenced by the overlapping area between the gate electrode and the source/drain region.
Innovation Solution
Incorporating insulating layers under and/or above the source/drain regions to reduce the overlapping area with the gate electrode, thereby reducing the parasitic capacitance by minimizing the thickness of the source/drain regions in specific portions, and ensuring electrical connections through top and bottom contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode overlaps with the source/drain region to ensure proper transistor operation, then the transistor can function correctly, but parasitic capacitance increases and AC performance deteriorates
Solution Approach 1:
The source/drain region is divided into multiple segments along the channel direction, with insulating layers positioned between them. This segmentation reduces the continuous overlapping area between the gate electrode and source/drain region, thereby reducing parasitic capacitance while maintaining electrical functionality through the insulating layers that provide electrical isolation.
Solution Approach 2:
Insulating layers are introduced as intermediary elements between the gate electrode and source/drain region. These insulating layers act as mediators that reduce the direct overlap and parasitic capacitance while still allowing the transistor to function through controlled electrical isolation and connection via contacts.
2Object-generated harmful factors
If the source/drain region thickness is reduced to minimize overlapping area, then parasitic capacitance decreases, but electrical connection and conductivity may be compromised
Solution Approach 1:
The source/drain region is segmented with insulating layers positioned between segments, allowing reduced thickness in overlapping areas while maintaining electrical connectivity through strategically placed contacts that bridge the segmented regions.
Solution Approach 2:
The source/drain region exhibits varying thickness characteristics at different locations: thinner in regions where the gate electrode overlaps to reduce parasitic capacitance, and thicker or connected via contacts in regions where electrical connection is critical, ensuring both reduced capacitance and maintained conductivity.
3Object-generated harmful factors
If insulating layers are added under and/or above source/drain regions to reduce parasitic capacitance, then AC performance improves, but device structure and manufacturing complexity increase
Solution Approach 1:
The source/drain region is segmented by introducing insulating layers at specific positions, creating a multi-layer structure that reduces parasitic capacitance. This segmentation approach systematically manages the increased structural complexity by organizing insulating layers at critical interfaces.
Solution Approach 2:
Insulating layers are added in the vertical dimension (under and/or above source/drain regions) rather than only in the horizontal plane, reducing parasitic capacitance through three-dimensional structural optimization while managing complexity through vertical integration.
Data Source
AI summary
Integrated circuit devices and methods of forming the same are provided. An integrated circuit device may include a substrate and a transistor stack on the substrate, the transistor stack including a first transistor and a second transistor on the first transistor. The first transistor may be between the substrate and the second transistor and the first transistor may include first and second source/drain regions, a first channel region between the first and second source/drain regions, and a first gate structure on the first channel region. A lower surface of the first source/drain region may be higher than a lower surface of the first gate structure relative to the substrate.