Stacked FET Multi-Height Cells With Power-Line Channel Overlap
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Solution Overview
Problem
In integrated circuit devices, multi-height standard cells with stacked field-effect transistors face challenges due to channel regions not overlapping power lines, which restricts effective channel width and increases contact complexity, impeding performance.
Innovation Solution
The integration of stacked field-effect transistors in multi-height standard cells where the lower or upper channel regions are merged to overlap the power line, increasing effective channel width and reducing contact complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If channel regions are kept separate from power lines in multi-height standard cells, then manufacturing simplicity is maintained, but effective channel width is restricted and contact complexity increases
Solution Approach 1:
The patent applies dimensionality change by allowing channel regions to overlap power lines in the vertical dimension (thickness direction) while maintaining horizontal separation in the planar layout. This resolves the contradiction by transitioning from two-dimensional separation to three-dimensional overlapping, thereby increasing effective channel width without complicating the manufacturing process.
Solution Approach 2:
The patent merges the channel regions with power lines in the vertical dimension by forming channel regions that extend through and overlap the power lines in the thickness direction. This merging approach increases the effective channel width while maintaining manufacturing simplicity, as the overlapping structure is formed through standard fabrication processes.
2Productivity
If channel regions overlap power lines in multi-height standard cells, then effective channel width is increased, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension to resolve this contradiction by forming channel regions that overlap power lines in the thickness direction. This allows effective channel width to be increased without requiring complex manufacturing processes, as the overlapping is achieved through standard vertical stacking techniques rather than complex lateral patterning.
Solution Approach 2:
The patent makes the channel regions multi-functional by having them serve both as conductive paths and as structures that overlap power lines for enhanced width. This universal approach allows the same channel region structure to achieve both electrical functionality and increased effective width without requiring additional manufacturing steps.
3Quantity of substance
If stacked field-effect transistors are used in multi-height cells, then integration density is increased, but channel regions fail to overlap power lines reducing performance
Solution Approach 1:
The patent resolves this contradiction by transitioning from planar channel region layout to vertical overlapping with power lines. The channel regions are formed to extend in the thickness direction and overlap the power lines, thereby maintaining high integration density through stacked transistor architecture while simultaneously improving device performance through increased effective channel width.
Solution Approach 2:
The patent merges the channel regions with power lines in the vertical dimension, allowing the stacked field-effect transistor structure to achieve both high integration density and improved performance. The merging occurs through the channel regions extending through and overlapping the power lines, creating a unified structure that serves both integration and performance goals.
Data Source
AI summary
Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include an upper transistor including an upper channel region on a substrate, a lower transistor between the substrate and the upper transistor, the lower transistor including a lower channel region, and a power line extending longitudinally in a first horizontal direction. At least one of the upper channel region or the lower channel region may extend longitudinally in a second horizontal direction that traverses the first horizontal direction, and the at least one of the upper channel region or the lower channel region may overlap the power line in a thickness direction.