3D Stacked FET Layout for Channel Width Without Taller Cells

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Solution Overview

Problem

Existing three-dimensional (3D) stacked Field Effect Transistors (FETs) face challenges in securing a sufficient channel width without increasing the cell height, which is crucial for high operating speed and operational accuracy in semiconductor devices.

Innovation Solution

The design incorporates a back-side wiring layer with alternating power and signal lines, a stacked structure of PMOS and NMOS FETs sharing a gate, and a front-side wiring layer with through-electrodes connecting the FETs, allowing for a channel width to be secured without increasing the cell height by omitting one through electrode in the unit cell.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If FETs are stacked in a three-dimensional structure to increase integration density, then device integration is improved, but channel width is reduced

Engineering Contradiction:

Improveintegration densityVSAvoidchannel width

Core Design Contradiction:

ProductivityVSLength of moving object

Solution Approach 1:

The patent transitions from planar FET arrangement to three-dimensional stacking, utilizing the vertical dimension to increase integration density while maintaining adequate channel width through optimized vertical spacing and gate structure design

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If through-electrodes are added to connect stacked FETs, then electrical connectivity is improved, but cell height increases

Engineering Contradiction:

Improveelectrical connectivityVSAvoidcell height

Core Design Contradiction:

ReliabilityVSLength of stationary object

Solution Approach 1:

The patent combines multiple through-electrode functions into shared structures, where through-electrodes serve both as inter-layer connectors and as part of the gate structure, thereby achieving electrical connectivity without proportionally increasing cell height

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Through-electrodes are designed to perform multiple functions simultaneously: providing electrical connectivity between stacked FETs, serving as gate structures, and acting as structural support elements, thereby reducing the need for additional dedicated height-consuming components

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentEP4407670A1Three-dimensional stacked field effect transistor

Publication Date: 2024.07.31 SAMSUNG ELECTRONICS CO LTD

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Figure 2B

AI summary

A 3D stacked FET (100) may include a back-side wiring layer (110) including a first back-side power line (112) and a second back-side power line (114), a first FET (120) on the back-side wiring layer (110), a second FET (130) over the first FET (120), a front-side wiring layer (140) over the second FET (130), a first through-electrode (150) connecting the first FET (120) to the second FET (130),. The front-side wiring layer (140) extends in a first direction and includes a front-side power line (142) connected to the second back-side power line (142) by a second through electrode (160). The first FET (120) and the second FET (130) share a gate (Gc) extending in a second direction perpendicular to the first direction. Each of the first FET (120) and the second FET (130) includes a source (S1, S2) and a drain (D1, D2) respectively on either side of the gate (Gc) in the first direction, and a channel (MBC1, MBC2) between the source and the drain and surrounded by the gate (Gc).