Stacked FET Common Gate Formation Without Vertical Gate Vias
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Solution Overview
Problem
Existing methods for forming a sequential CFET with electrically connected top and bottom gate electrodes face complications, necessitating an improved approach to facilitate efficient circuitry design.
Innovation Solution
A method for forming a stacked FET device involves forming a bottom FET with a source, drain, and a bottom gate electrode, followed by a bonding layer, and then a top FET with a fin structure and dummy gate, using etching and spacer layers to create a common gate electrode by isotropic etching, allowing direct contact between the top and bottom gate electrodes without increased side extensions, thereby reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a vertical top-to-bottom-gate-via is formed to connect gates in a sequential CFET, then electrical connection between top and bottom gates is achieved, but the manufacturing process becomes complicated
Solution Approach 1:
The patent transitions from a vertical via connection approach to a lateral connection approach where the bottom gate electrode extends laterally underneath the top FET channel. This dimensional change eliminates the need for complex vertical vias through the bonding layer, simplifying the manufacturing process while maintaining electrical connectivity between top and bottom gates.
Solution Approach 2:
The patent introduces a dummy gate structure as an intermediary element that facilitates the lateral extension of the bottom gate electrode. The dummy gate serves as a placeholder and structural mediator during the formation process, enabling the bottom gate to extend underneath the top FET without requiring complex via formation through the bonding layer.
2Reliability
If side gate extensions are increased to form common gate electrode, then gate connectivity is improved, but parasitic capacitance increases
Solution Approach 1:
Instead of extending gates laterally along the channel (increasing side extensions), the patent extends the bottom gate electrode laterally underneath the channel in a different spatial dimension. This approach improves gate connectivity and increases the effective gate area without adding parasitic capacitance from side extensions, as the extension is positioned underneath rather than alongside the channel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of a common gate electrode with increased cross-sectional area and reduced resistivity, improving the connectivity and efficiency of the stacked FET device.
Implementation Method 1
removing the bonding layer pattern portion by subjecting the bonding layer pattern portion to an isotropic etching process via the upper gate cavity
Implementation Method 2
epitaxially growing source/drain bodies on the exposed end surfaces of the channel layer
Data Source
AI summary
A method for forming a stacked field-effect transistor device is provided. The method including: forming a bottom FET device comprising a bottom gate electrode arranged; forming a bonding layer of dielectric bonding material over the bottom FET device; and forming a top FET device on the bonding layer, including: forming a fin structure comprising a channel layer; etching through the bonding layer to form a bonding layer pattern comprising the dielectric bonding material underneath the fin structure; forming a dummy gate and a dummy gate spacer layer; forming cuts in the fin structure and the bonding layer pattern; forming recesses underneath a fin structure portion preserved underneath the dummy gate by laterally etching back side surface portions of a bonding layer pattern portion; removing the first spacer layer and subsequently forming a second spacer layer covering the side surfaces of the dummy gate and filling the recesses; removing the dummy gate selectively to the second spacer layer to form an upper gate cavity portion exposing the fin structure portion; forming a lower gate cavity portion exposing an upper surface of the bottom gate electrode, comprising removing the bonding layer pattern portion by subjecting the bonding layer pattern portion to an isotropic etching process via the upper gate cavity; and forming a gate electrode in the upper and lower gate cavity portions.